P. Agnello

Publications (30)5.75 Total impact

• Conference Proceeding: Reviving knowledge and preventing accidents in process industries

  P. Agnello, S. Ansaldi, P.A. Bragatto, P. Pittiglio
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  ABSTRACT: In process industries the safety knowledge is well defined and formalized. The safety management systems, with related documents, is the internal safety knowledge repository. Standard codes, guide lines and good practices are the repository of shared knowledge within industries. In these industries the most accidents do not happen because a lack of knowledge, but because it has been ignored, or forgotten, or misunderstood, or misapplied by the operators. A terrific accidents reduction could be achieved by keeping alive the operational safety knowledge in industrial establishments. In plant operation, even though hazards are accurately identified and analyzed, failures, deviation, losses and other unexpected events are much more usual than accidents. These events, even without consequences, are essential for the safety management, as they may reveal the disruptions in practical operator knowledge. A knowledge management model is proposed to revive the operational knowledge, stimulated by the discussion of the unexpected events. If required, the internal proprietary knowledge may be reviewed by exploiting in a better way the shared knowledge, which is hidden in good practices and other shared documents. The model has been implemented by means of advanced information management tools and applied in a industrial facility.
  Industrial Engineering and Engineering Management, 2009. IEEM 2009. IEEE International Conference on; 01/2010
• Conference Proceeding: Access Transistor Design and Optimization for 65/45nm High Performance SOI eDRAM

  G Wang, P. Parries, K Cheng, K. Amarnath, J Cai, G. Freeman, P. Agnello, S.S. Iyer
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  ABSTRACT: A 65 nm prototype embedded DRAM macro on partially depleted SOI (PD-SOI) substrate capable of <2. 0ns latency and the enabling cell technology have been described previously [1,2]. In this paper, we focus on the cell design and optimization for best retention and performance which have been extended to the 45 nm node.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
• Conference Proceeding: (110) channel, SiON gate-dielectric PMOS with record high I on =1 mA/¿m through channel stress and source drain external resistance (R ext ) engineering

  B Yang, A Waite, H Yin, J Yu, L. Black, D. Chidambarrao, A. Domenicucci, X Wang, S.H. Ku, Y Wang, [......], D Park, C. Sung, R. Wachnik, G. Freeman, D. Schepis, E. Maciejewski, M. Khare, E. Leobandung, S. Luning, P. Agnello
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  ABSTRACT: This paper presents for the first time (110) PMOS characteristics without R_ext degradation, allowing investigation of fundamental mobility and demonstration of drive current I_on in excess of 1mA/mum at I_off =100 nA/mum.
  Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
• Conference Proceeding: Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

  B.F. Yang, K. Nummy, A. Waite, L. Black, H. Gossmann, H. Yin, Y. Liu, B. Kim, S. Narasimha, P. Fisher, [......], C. Sheraw, D. Wehella-gamage, J. Holt, X. Chen, D. Park, C.Y. Sung, D. Schepis, M. Khare, S. Luning, P. Agnello
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  ABSTRACT: This work demonstrates that the ~2times mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress. (110) PMOS with 3.5 GPa compressively stressed liners demonstrate strong channel drives with I_on=800 muA/mum at I_off=100 nA/mum (V_dd=10 V) for 190 nm poly-pitch, the highest reported to date for 45-nm-node (110) PMOS using conventional gate dielectrics without eSiGe stressors. Additionally, (110) PMOS show better scalability, with 15% smaller total I_on degradation than (100) PMOS when poly-pitch scales from 250 nm to 190 nm.
  VLSI Technology, 2007 IEEE Symposium on; 07/2007
• Conference Proceeding: CMOS Fabricated by Hybrid-Orientation Technology (HOT)

  Bin Yang, M Yang, D.M. Fried, C. D. Sheraw, A Waite, K. Nummy, L. Black, S.D. Kim, H Yin, B Kim, S. Narasimha, X Chen, M. Khare, S. Luning, P. Agnello
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  ABSTRACT: Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence, as well as the high Rext issue for (110) PMOS are discussed in this paper.
  Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on; 07/2007
• Source

  Available from: Werner Rausch

  Conference Proceeding: High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

  S. Narasimha, K. Onishi, H.M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, [......], Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, P. Agnello
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  ABSTRACT: We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum², and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Source

  Available from: Vincent Mcgahay

  Conference Proceeding: High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

  W.-H. Lee, A. Waite, H. Nii, H.M. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, L. Black, R. Bolam, [......], P. Press, K. Frohberg, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, M. Raab, D. Greenlaw, N. Kepler
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  ABSTRACT: A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (V_dd=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum₂
  Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
• Conference Proceeding: High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

  E. Leobandung, H. Nayakama, D. Mocuta, K. Miyamoto, M. Angyal, H.V. Meer, K. McStay, I. Ahsan, S. Allen, A. Azuma, [......], G. Freeman, S.-F. Huang, T. Ivers, H. Kuroda, D. McHerron, J. Pellerin, Y. Toyoshima, S. Subbanna, N. Kepler, L. Su
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  ABSTRACT: A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm² SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.
  VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
• Conference Proceeding: Dual stress liner enhancement in hybrid orientation technology

  C.D. Sheraw, M. Yang, D.M. Fried, G. Costrini, T. Kanarsky, W.-H. Lee, V. Chan, M.V. Fischetti, J. Holt, L. Black, [......], D. Chidambarrao, X. Wang, A. Bryant, D. Brown, C.-Y. Sung, P. Agnello, M. Ieong, S.-F. Huang, X. Chen, M. Khare
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  ABSTRACT: Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I_DSat at 100 nA/um I_OFF for V_DD=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.
  VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
• Conference Proceeding: Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

  H.S. Yang, R. Malik, S. Narasimha, Y. Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J.C. Arnold, K. Bandy, [......], R. van Bentum, G. Grasshoff, C. Schwan, E. Ehrichs, S. Goad, J. Buller, S. Krishnan, D. Greenlaw, M. Raab, N. Kepler
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  ABSTRACT: For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.
  Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
• Conference Proceeding: High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

  H. Park, W. Rausch, H. Utomo, K. Matsumoto, H. Nii, S. Kawanaka, P. Fisher, S.-H. Oh, J. Snare, W. Clark, [......], M. Tsukamoto, Y. Kohyama, J. Cheek, I. Yang, H. Kuroda, Y. Toyoshima, J. Pellerin, D. Schepis, P. Agnello, J. Welser
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  ABSTRACT: We present enhanced 90 nm node CMOS devices on a partially depleted SOI with 40 nm gate length, featuring advanced process modules for manufacture, including RSD (raised source/drain), disposable spacer, final spacer for S/D doping and silicide proximity, NiSi, and thermally optimized MOL (middle-of-line) process. For the first time, we systematically designed silicide proximity in SOI and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 μA/um and 420 μA/um at Ioff = 40 nA/um with Vdd = 1.0 V, for NFET and PFET, respectively), significant reduction in effective gate oxide thickness under gate inversion by ∼1.2 Å and ∼2.1 Å, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.
  Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
• Conference Proceeding: A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

  M. Khare, S.H. Ku, R.A. Donaton, S. Greco, C. Brodsky, X. Chen, A. Chou, R. DellaGuardia, S. Deshpande, B. Doris, [......], W. Yan, E. Barth, R. Ferguson, P. Gilbert, D. Schepis, A. Sekiguchi, R. Goldblatt, J. Welser, K.P. Muller, P. Agnello
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  ABSTRACT: This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.
  Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
• Conference Proceeding: Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

  B.H. Lee, A. Mocuta, S. Bedell, H. Chen, D. Sadana, K. Rim, P. O'Neil, R. Mo, K. Chan, C. Cabral, [......], A. Domenicucci, K.A. Jenkins, S. Narasimha, S.H. Ku, M. Ieong, I.Y. Yang, E. Leobandung, P. Agnello, W. Haensch, J. Welser
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  ABSTRACT: High quality ultra-thin TM-SGOI substrate with T_SOI < 55 nm is developed to combine the device benefits of strained silicon and SOI. 80-90% Id,sat and electron mobility increase are shown in long channel nFET device. For the first time, 20-25% device performance enhancement is demonstrated at 55 nm short channel strained silicon SGOI nFET devices.
  Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
• Conference Proceeding: Thickness measurement of ultra-thin gate dielectrics under inversion condition

  W.J. Zhu, M. Khare, J. Snare, P.R. Varekamp, S.H. Ku, P. Agnello, T.C. Chen, T.P. Ma
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  ABSTRACT: Accurate measurement of inversion thickness is essential in ULSI technology for development and control of ultra-thin gate dielectric processes. However, the accuracy of the measurement can be severely affected by the high gate leakage current and series resistance. This paper presents a methodology to reduce the measurement error by optimizing the ac modulation frequency and test device structures
  VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on; 02/2001
• Conference Proceeding: A high performance 0.13 μm SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

  J.W. Sleight, P.R. Varekamp, N. Lustig, J. Adkisson, A. Allen, O. Bula, X. Chen, T. Chou, W. Chu, J. Fitzsimmons, [......], S. Womack, E. Barth, G. Biery, C. Davis, R. Ferguson, R. Goldblatt, E. Leobandung, J. Weiser, I. Yang, P. Agnello
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  ABSTRACT: This paper describes a second generation 1.2 V high performance 0.13 μm SOI technology. Aggressive ground rules and a tungsten damascene local interconnect render the densest 6T 0.13 μm SRAM reported to date with a cell area of 1.80 μm². 248 nm lithography is used for all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced BEOL process with low-k interlevel dielectrics and SiC barrier layers
  Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
• Conference Proceeding: High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

  S. Narasimha, A. Ajmera, H. Park, D. Schepis, N. Zamdmer, K.A. Jenkins, J.-O. Plouchart, W.-H. Lee, J. Mezzapelle, J. Bruley, B. Doris, J.W. Sleight, S.K. Fung, S.H. Ku, A.C. Mocuta, I. Yang, P.V. Gilbert, K.P. Muller, P. Agnello, J. Welser
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  ABSTRACT: This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uA/um (NFET, 1171 uA/um dynamic) and 490 uA/um (PFET, 507 uA/um dynamic) at I_off levels of 100 nA/um for 1.1 volt operation. The physical gate length (L_poly) for these devices is 39 nm. The saturation currents increase to 1180 uA/um and 540 uA/um at I_off levels of 300 nA/um, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f_max of 193 GHz has been demonstrated along with an f_T of 178 GHz
  Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
• Conference Proceeding: Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

  S.K.H. Fung, M. Khare, D. Schepis, Woo-Hyeong Lee, Suk Hoon Ku, H. Park, J. Snare, B. Doris, A. Ajmera, K.P. Muller, P. Agnello, P. Gilbert, J. Welser
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  ABSTRACT: High performance SOI CMOS designed for the 100 nm technology node is presented. At 1 V supply voltage, the 33 nm devices give a drive current of 1000 (1100) μA/μm DC (dynamic) for NFET and 445 (457) μA/μm for PFET at an off current of 300 nA/μm. The intrinsic gate delays are 0.55 ps and 1.19 ps. The NFET delay is further reduced to 0.45 ps at gate length scaled to 25 nm. The delay and current values are the best ever reported at 1.0 V. The excellent result is accomplished by using super-HALO design on 45 nm SOI substrate
  Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
• Conference Proceeding: A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

  P. Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, [......], C. Yu, P. Agnello, J. Connolly, S. Crowder, C. Davis, R. Ferguson, A. Sekiguchi, L. Su, R. Goldblatt, T.C. Chen
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  ABSTRACT: This paper describes a 1.2V high performance 0.13 μm generation SOI technology. Aggressive ground-rules and a tungsten damascene local interconnect render the densest 6T SRAM reported to date with a cell area of 2.16 μm². This is accomplished with 248nm lithography, using optical proximity correction and resolution enhancement techniques on all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced low-k interlevel dielectric
  VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
• Conference Proceeding: A 0.18 μm high-performance logic technology

  S. Crowder, S. Greco, H. Ng, E. Barth, K. Beyer, G. Biery, J. Connolly, C. DeWan, R. Ferguson, X. Chen, [......], A. Ray, D. Ryan, K. Tallman, T. Wagner, V. McGahay, E. Crabbe, P. Agnello, R. Goldblatt, L. Su, B. Davari
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  ABSTRACT: In this paper, we describe a high-performance 0.18 μm logic technology with dual damascene copper metallization and dense SRAM memory. Local interconnect technology allows us to fabricate SRAM cells as small as 3.84 μm². We demonstrate that copper metallization continues to exhibit performance advantages over aluminum-based technologies in this generation
  VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
• Conference Proceeding: Sub-60 nm physical gate length SOI CMOS

  I.Y. Yang, K. Chen, P. Smeys, J. Sleight, L. Lin, M. Leong, E. Nowak, S. Fung, E. Maciejewski, P. Varekamp, W. Chu, H. Park, P. Agnello, S. Crowder, F. Assaderaghi, L. Su
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  ABSTRACT: This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of silicon film thickness. A high performance SOI CMOS with well-behaved 52 nm gate length devices is demonstrated
  Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999