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T. Nogami,
T. Bolom,
A. Simon,
B-Y. Kim,
C-K. Hu,
K. Tsumura,
A. Madan,
P. Flaitz,
F. H. Baumann,
C. Parks, [......],
S-T. Chen,
T. Vo,
J. Kelly,
O. Straten,
C. Penny,
G. Bonilla,
J. Wynne,
P. Kozlowski,
T. Spooner,
D. Edelstein
Electron Devices Meeting, 2010. IEDM '10 Technical Digest., International. 12/2010;
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ABSTRACT: Co films were selectively deposited as Cu capping layers by chemical-vapor-deposition technique. X-ray fluorescence spectroscopy determined the Co deposition selectivity as a function of the deposition temperature and substrate materials. The Co/Cu interfacial property was characterized and revealed no detectable oxygen at the interface. The selectivity of the Co deposition process and the property of the resulted Co/Cu interface were further confirmed with time-dependent-dielectric-breakdown and electromigration tests.
IEEE Electron Device Letters 08/2010; · 2.85 Impact Factor
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ABSTRACT: As the current-carrying capability of a copper line is reduced due to interconnect dimension shrinkage, self-aligned CoWP metal-cap has been reported to be helpful to improve degraded electromigration (EM) reliability. However, adoption of this new metal cap in general further exacerbates the already problematic low-k dielectric TDDB reliability at 32nm and beyond. This paper provides a comparative study of ULK conduction mechanisms over a wide range of temperature (30°C to 295°C) and TDDB acceleration kinetics at 125°C for Cu interconnects with and without CoWP metal cap at 32nm technology. It was found that adding CoWP didn't change the fundamental ULK leakage conduction mechanism and TDDB kinetics if its process was optimized. Comparable leakage and TDDB performance were achieved with an optimized CoWP process.
Interconnect Technology Conference (IITC), 2010 International; 07/2010
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ABSTRACT: This letter evaluates the electrical and reliability performances of a back-end-of-line Cu/ultralow- k (ULK) dielectric interconnect with features of gouged via and damage-free profile. The interconnect structure in ultralarge-scale integrated circuits forms vias between successive layers by forming first the via opening within the ULK dielectric, followed by forming the via-gouging feature and then the line opening. This fabrication approach does not disrupt the coverage of the deposited trench diffusion barrier in a line opening and does not introduce dielectric profile damages caused by creating the via-gouging feature. The resulting interconnect structure maintains the gouged-via feature without any profile damage, which not only improves the overall integrity of the integrated circuit but also shows time-dependent dielectric-breakdown performance enhancement over the conventional interconnect structure.
IEEE Electron Device Letters 05/2010; · 2.85 Impact Factor
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ABSTRACT: In this paper, a correlation between the I-V slope at low fields and TDDB voltage acceleration is demonstrated for the first time, based on a wide range of data from 32 nm to 130 nm node hardware. The data supports the radicE model, which is based on electron fluence (leakage current) driven, Cu catalyzed, low-k dielectric breakdown. Using this correlation, a fast wafer level screen method was also implemented for process improvement and TDDB reliability monitoring.
Interconnect Technology Conference, 2009. IITC 2009. IEEE International; 07/2009
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F. Chen,
M. Shinosky,
B. Li,
J. Gambino,
S. Mongeon,
P. Pokrinchak,
J. Aitken,
D. Badami,
M. Angyal,
R. Achanta,
G. Bonilla,
G. Yang,
P. Liu,
K. Li,
J. Sudijono,
Y. Tan,
T.J. Tang,
C. Child
[show abstract]
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ABSTRACT: During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new ldquofatalrdquo via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the ldquofatalrdquo via ratio.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
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Z.X. He,
D. Daley,
R. Bolam,
D. Vanslette, F. Chen,
E. Cooney,
D. Mosher,
N. Feilchenfeld,
K. Newton,
E. Eshun,
R. Rassel,
J. Benoit,
D. Coolbaugh,
S. St. Onge,
J. Dunn
[show abstract]
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ABSTRACT: Two MIM capacitors with capacitance density of 11 and 0.48 fF/um<sup>2</sup> were fabricated simultaneously using IBM-s 0.13 um SiGe 8 WL BiCMOS process. Results from DC parametric measurement indicate that these two capacitors compliment each other extremely well.
Bipolar/BiCMOS Circuits and Technology Meeting, 2008. BCTM 2008. IEEE; 11/2008
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ABSTRACT: Low-k time-dependent dielectric breakdown (TDDB) is rapidly becoming one of the most important reliability issues in Cu/low-k technology development and qualification. Although considerable progress has been made in recent years in addressing the electric field dependence of low-k time-to-breakdown (tBD), there has been very little comprehensive work done on the effect of metal area and line spacing on low-k TDDB. The lifetime of a product chip is typically obtained by extrapolating TDDB data from small test structures to large chip areas, and the low-k TDDB line spacing scaling rule normally should be considered for the definition of operating voltages for various technologies to assure long-term reliability. Therefore, both area scaling and line spacing scaling relations are of great importance, in order to have a robust technology qualification. In this study, a thorough investigation into the 45 nm low-k SiCOH TDDB was conducted in order to understand the breakdown failure statistics, to model the area dependence, and to explore the line spacing scaling. With the help of experimental results and computational simulations, the effect of line-to-line spacing on low-k TDDB was clearly identified and a methodology for accurate determination of Weibull shape factor is proposed.
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
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V. McGahay,
G. Bonilla, F. Chen,
C. Christiansen,
S. Cohen,
M. Cullinan-Scholl,
J. Demarest,
D. Dunn,
B. Engel,
J. Fitzsimmons, [......],
H. Shobha,
E. Simonyi,
J. Widodo,
A. Grill,
R. Hannon,
M. Lane,
H. Nye,
T. Spooner,
R. Wisnieff,
T. Ivers
[show abstract]
[hide abstract]
ABSTRACT: A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and process-induced damage were successfully overcome. Yield and interconnect reliability metrics comparable to dense K=3 SiCOH have been achieved. Package deep thermal cycle showed sensitivity to assembly which is controllable though chip edge structural engineering
Interconnect Technology Conference, 2006 International; 07/2006
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ABSTRACT: This paper introduces an efficient algorithm to reconstruct heart rate signal based on an integral pulse frequency modulation (IPFM) model. The heart rate signal was reconstructed by the summation of a set of sine functions with different weights, whose value could be determined from the IPFM process. Simulation study demonstrated that the signal reconstructed by the proposed method would preserve high frequency component with less distortion than the popular derivative of cubic spline interpolation (DCSI) method. When applied to the spectral analysis of heart rate variability (HRV) of simulated heart rate signal, the proposed method achieved smaller bias than the DCSI method. Therefore, the proposed method would be beneficial for the reconstruction of heart rate signal and the relevant spectral analysis of HRV in the future
Engineering in Medicine and Biology Society, 2005. IEEE-EMBS 2005. 27th Annual International Conference of the; 02/2006
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Microelectronics Reliability. 01/2006; 46:232-243.
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M. Fukasawa,
S. Lane,
M. Angyal,
K. Chanda, F. Chen,
C. Christiansen,
J. Fitzsimmons,
J. Gill,
K. Ida,
K. Inoue, [......],
I. Melville,
M. Minami,
S. Nguyen,
C. Penny,
A. Sakamoto,
Y. Shimooka,
M. Ono,
D. McHerron,
T. Nogami,
T. Ivers
[show abstract]
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ABSTRACT: This paper describes a comprehensive characterization of a 65 nm, 300 mm wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of the SiCOH material and precise process optimization enable the minimization of layer damage during etching and strip processes. 3D modeling reveals that the k-value of the SiCOH material was maintained at its initial value after the integration. Electrical yield, reliability and chip-to-package (CPI) evaluation are also presented. The results were comparable with the conventional SiCOH integration scheme.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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F. Chen,
K. Chanda,
I. Gill,
M. AngyaI,
J. Demarest,
T. Sullivan,
R. Kontra,
M. Shinosky,
J. Li,
L. Economikos, [......],
K. Urata,
T. Bolom,
K. Inoue,
J. Smith,
Y. Ishikawa,
M. Naujok,
P. Ong,
A. Sakamoto,
D. Hunt,
J. Aitken
Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International; 02/2005
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[show abstract]
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ABSTRACT: The combination of low k dielectric material application and aggressive scaling in advanced interconnects creates new challenges for thermal and electromigration solutions. The complexity and difficulty are discussed for modeling and evaluating thermal and EM interactions in circuit designs. A few examples are given to show quantitatively the impact of different dielectric materials on maximum allowed current density and scaling in Cu lines.
Integrated Reliability Workshop Final Report, 2004 IEEE International; 11/2004
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F. Chen,
J. Gill,
D. Harmon,
T. Sullivan,
B. Li,
A. Strong,
H. Rathore,
D. Edelstein,
C.-C. Yang,
A. Cowley,
L. Clevenger
[show abstract]
[hide abstract]
ABSTRACT: Accurate specification of design groundrules for interconnect systems requires knowledge of the thermal behavior of the systems. A key parameter that characterizes the thermal behavior is the thermal conductivity of the inter-level dielectric (ILD). In practical VLSI applications, the metal interconnects are fully embedded in a stacked, composite ILD media, which presents difficult challenges for the accurate determination of thermal conductivity. In this paper, we propose the concept of an "effective thermal conductivity" to model such complicated, composite media, and introduce a simple methodology to accurately measure effective and bulk thermal conductivities of various thin dielectric layers in integrated circuits. We present measured effective conductivities of several composite media, including various Cu/low-k dielectric configurations such as Cu/SiCOH, Cu/SiLK<sup>®</sup>, Cu/fluorinated silicate glass (FSG), and a hybrid stack with Cu lines in SiLK<sup>®</sup> and Cu vias in un-doped silicate glass (USG). Measurements were recorded in the temperature range from 30°C to 120°C using a unique combination of fully embedded Cu lines as heater/thermometers, wafer-level temperature vs. power (TVP) measurements, and the Harmon-Gill (H-G) quasi-analytical heat conduction model. The thermal conductivities of all the films studied here were observed to increase with rising substrate temperature.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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D. Edelstein,
H. Rathore,
C. Davis,
L. Clevenger,
A. Cowley,
T. Nogami,
B. Agarwala,
S. Arai,
A. Carbone,
K. Chanda, [......],
E. Simonyi,
A. Swift,
T. Van Kleeck,
S. Vogt,
Y.-Y. Wang,
W. Wille,
J. Wright,
C.-C. Yang,
M. Yoon,
T. Ivers
[show abstract]
[hide abstract]
ABSTRACT: Integration and development of Cu Back-End of Line (BEOL) with PECVD low-k organosilicate glass (OSG, also called SiCOH, carbon-doped oxide, CDO, etc.) for 130 nm and 90 nm CMOS technologies has been reported by a number of institutions. Here we report on a Cu/SiCOH technology which has similarities, but also enhanced integration and reliability characteristics while preserving the R and C performance levels. These enhancements have led to excellent reliability results reported here, and are expected to increase the robustness to high-volume manufacturing and extendibility to next-generation smaller dimensions. The SiCOH and cap mechanical, chemical, and electrical strengths are increased, as well as associated interfacial adhesions. These combine with an optimized Cu metallization. As chip-package reliability is most at risk for low-k dielectrics, improvements have been brought into the BEOL level structure, the kerf design, and in some cases new packaging materials. When combined with the dielectric material and interface improvements, redundancy exists in the protection against potential chip-packaging failures. No failures occur in the full rounds of chip-package reliability stress testing done here on multiple wirebond and flip-chip packages. These packaging and other reliability results are presented, including BEOL-specific tests [electromigration (E-M), stress-migration (S-M), time-dependent dielectric breakdown (TDDB), thermal cycling (T/C)], environmental [temperature-humidity-bias (THB)], and functional stressing of product modules. The stress criteria and results exceeded JEDEC standards. All Cu/SiCOH tests passed at the same levels as our concurrent 90 nm Cu/SiOF technology.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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F. Chen,
J.R. Lloyd,
K. Chanda,
R. Achanta,
O. Bravo,
A. Strong,
P.S. McLaughlin,
M. Shinosky,
S. Sankaran,
E. Gebreselasie,
A.K. Stamper,
Z.X. He
[show abstract]
[hide abstract]
ABSTRACT: The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International;
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[show abstract]
[hide abstract]
ABSTRACT: With the wide application of low-k and ultra-low-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low-k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low-k technology development because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO2 dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this paper, three critical issues of low-k TDDB characteristics during low-k development and qualification will be reviewed. In the first part, a low-k TDDB field acceleration model and its determination will be discussed. In the second part, low-k dielectric time-to-breakdown (tBD) statistical distribution and TDDB area scaling law for reliability projection will be examined. In the last part, as low-k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low-k TDDB degradation will be demonstrated. Some key aspects which need to be carefully addressed to control overall low-k TDDB performance from process and integration side will be discussed.
Microelectronics Reliability.
