[Show abstract][Hide abstract] ABSTRACT: We report an experimental study of the defects induced by a TiN metal gate. Nitrogen-induced defects due to diffusion from the nitrided gate have been evidenced. The energy profile of the density of interface states in the silicon band gap has been extracted by original spectroscopic charge pumping measurements. We have identified two specific peaks near the Si band edges as the signature of N diffusion. The density of defects has then been correlated to the electron mobility degradation and compared to a theoretical model which well reproduces the experimental data.
Solid-State Electronics 11/2011; s 65–66:139–145. · 1.51 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper investigates Carbon-doped GeTe (GeTeC) as novel material for Phase-Change Memories (PCM). In the first part of the manuscript, a study of GeTeC blanket layers is presented. Focus is on GeTeC amorphous phase stability, which has been studied by means of optical reflectivity and electrical resistivity measurements, and on GeTeC structure and composition, analyzed by XRD and Raman spectroscopy. Then, electrical characterization of GeTeC-based PCM devices is reported: resistance drift, data retention performances, RESET current and power, and SET time have been investigated. Very good data retention properties and reduction of RESET current make GeTeC suitable for both embedded and stand-alone PCM applications, thus suggesting GeTeC as promising candidate to address some of the major issues of today’s PCM technology.
Solid-State Electronics 11/2011; s 65–66:197–204. · 1.51 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In this work comparative simulations and analysis of amorphization current are presented for pillar type and GST confined type PCRAM structures. The simulations are realized with the PCM model of Sentaurus Device using an analytical phase transition model coupled with a drift–diffusion electro-thermal model for the transport. The objectives of this work are the selection of optimized cell structures for reset conditions. It is confirmed that regarding Ireset the GST confined cell is more efficient than the pillar type. Our study points out that a compromise has to be found in some devices where the conditions of an optimized amorphous current correspond to a lowered resistivity contrast between the amorphous and crystalline states. A compromise has also to be found between optimal structures as designed by simulation and technological constraints associated to their fabrication.
[Show abstract][Hide abstract] ABSTRACT: The commercialization of Phase-Change Memories (PCM), based on the well-known GST compound, have been recently started, tailored for consumer applications. Despite other excellent performances (i.e. low-power, scalability,...), data retention is assured up to 85°C, still limited for the automotive market segment. Alternative active material able to comply with the stringent requirements of automotive applications should possibly exhibit higher crystallization temperature (T<sub>C</sub>) as well as higher Activation Energy (E<sub>A</sub>) with respect to GST. Recent literature shows that GeTe provides better retention, while several works put in evidence how data retention is enhanced by inclusions in pure host alloys.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
[Show abstract][Hide abstract] ABSTRACT: In this paper we present a study of Phase-Change non-volatile Memory (PCM) devices integrating carbon-doped GeTe as chalcogenide material. Carbon-doped GeTe, named GeTeC, remarkably lowers the RESET current and features very good data retention properties as well. In particular, GeTe PCM with 10% carbon inclusions (named GeTeC10%) yields about 30% of RESET current reduction with respect to pure GeTe and GST. Furthermore, our GeTeC10% memory cells are expected to guarantee a 10-years-lifetime-temperature of about 127°C, which is one of the highest ever reported for PCM. The outstanding properties of GeTeC make this material promising for non-volatile memory technologies.
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European; 10/2010
[Show abstract][Hide abstract] ABSTRACT: In this paper, we report on the properties of various phase change materials, namely GST, GeTe and GeTeC, for non volatile memory applications. As expected from thin films characterization, the high temperature data retention properties of the memory cells are improved when going from GST, to GeTe and hereafter GeTeC. The higher set speed of GeTe and the lower reset current of GeTeC are also highlighted.
European Symposium on Phase Change and Ovonic Science (E\PCOS), Milan; 09/2010
[Show abstract][Hide abstract] ABSTRACT: Transport mechanisms through SiO2/HfO2 gate stacks have been investigated by means of Capacitance–Voltage (C–V), Current–Voltage (I–V) in a large range of temperature (80–400 K) and Transmission Electron Microscopy (TEM) measurements, on several nMOS transistors featuring different interfacial layer and HfO2 thicknesses. The temperature dependency of experimental gate leakage currents have been found to be very weak when plotted versus total charge, except on thicker stacks, in inversion regime, between 300 and 400 K. Experiments have been compared with Direct Tunneling current (DT) simulations in inversion regime, using as few as possible arbitrary assumptions and fitting parameters. This comparison has shown that ultra-thin interfacial layer differs from pure SiO2 only below 1 nm thickness, confirming previous theoretical works.
[Show abstract][Hide abstract] ABSTRACT: In this work, we present a detailed investigation of the electrical characteristics of 3D Gate-All-Around (GAA) Silicon nanowire (down to 6nm-diameter) SONOS memories compared to standard planar SONOS devices. In particular, by means of TCAD simulations, the write, erase and retention characteristics under uniform FN stress are explained and the main geometrical and electrostatic effects of 3D cylindrical devices are put in evidence. The physical mechanisms dominating the 3D devices performance and reliability are identified. In particular, the great influence of band-to-band phenomenon in the erase characteristics is underlined.
[Show abstract][Hide abstract] ABSTRACT: This paper investigates material and electrical properties of a new chalcogenide alloy for Phase-Change Memories (PCM): Carbon-doped GeTe (named GeTeC). First, several physico-chemical, optical and electrical analyses have been performed on full-sheet chalcogenide depositions in order to understand the intrinsic GeTeC phase-change behavior, and to characterize structure and composition of amorphous and crystalline states. Then, GeTeC with two different Carbon doping (4% and 10%) has been integrated in pillar-type analytical PCM cells. Physico-chemical and electrical data indicate that GeTeC is characterized by a much more stable amorphous phase compared to undoped GeTe. Thus, GeTeC offers a slower programming speed versus GeTe, but an improved data retention at high temperature. Finally, we argue that GeTeC alloy is a promising candidate for future developments of PCM technologies for embedded applications.
[Show abstract][Hide abstract] ABSTRACT: In this letter, we present a study on the electrical behavior of phase-change memories (PCMs) based on a GeTe active material. GeTe PCMs show, first, extremely rapid SET operation (yielding a gain of more than one decade in energy per bit with respect to standard GST PCMs), second, robust cycling, up to 1 ?? 10<sup>5</sup>, with 30-ns SET and RESET stress time, and third, a better retention behavior at high temperature with respect to GST PCMs. These results, obtained on single cells, suggest GeTe as a promising alternative material to standard GST to improve PCM performance and reliability.
IEEE Electron Device Letters 06/2010; · 3.02 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The Phase Change Memory (PCM), is one of the most promising concepts, as a replacement of Flash memories that should be put in production in next years. However, even if the robustness of such technology is demonstrated for consumer stand-alone applications with typically GST as phase-change chalcogenide material, data retention at high temperature remains an issue, and seemingly even GST based alloys are not able to respect requirements of automotive embedded applications. That is why material research on alternative chalcogenide materials is still lacking, and thorough electrical characterization at analytical cell level is necessary to evaluate the performances of the integrated material. In this work we introduce this concept and the tests to evaluate new technological steps. In particular, we describe the test system optimization and we examine the full automated sequences used for statistic data collection. First step consist in acquiring the SET-toRESET and RESET-to-SET programming characteristics; then data retention tests follow and eventually the cycling experiment close the run. Several characteristics and graphs illustrate this work displaying the key parameters.
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on; 04/2010
[Show abstract][Hide abstract] ABSTRACT: In this paper, we have studied the charge trapping mechanisms of nitride-based non-volatile memories. The impact of different silicon-nitride (SiN) compositions (standard, std, and Si-rich) on the device characteristics has been investigated through material characterizations, electrical measurements, atomistic and electrical simulations. We found that the different physical nature of the dominant defects in the two SiN compositions is at the origin of the different device electrical behaviors. In particular, we argue that the different electron occupation number of the defect states of the two SiN materials explains the observed faster erasing speed and charge loss rate of Si-rich SiN devices, with respect to std SiN devices, in spite of comparable programming behavior. A simple trap model is proposed to improve state of the art simulators of SiN based memories.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
[Show abstract][Hide abstract] ABSTRACT: The paper presents an overview of the Bias Temperature Instabilities (BTI) reliability in High-k/Metal gate technologies. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.
[Show abstract][Hide abstract] ABSTRACT: Al incorporation in the High-κ/metal gate stack is studied for pMOS transistors application. Al is here incorporated before or after high-k deposition, or during the metal deposition. Using bevelled oxides and Internal photoemission (IPE), we discriminate and quantify the three key mechanisms shifting the effective metal workfunction WFMeff: (1) a dipole (up to ~1 eV!) build up at the SiO2/High-κ interface induced by Al diffusion; (2) a reduction of this dipole for small interfacial SiO2 layer; (3) an opposite shift of the metal workfunction WFM towards N+ for Metal-Al compounds.
International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2010;
[Show abstract][Hide abstract] ABSTRACT: PBTI in La-doped HfSiON/TiN stacks is investigated using Ultra Fast IV measurements. Excellent PBTI lifetime of these oxides is demonstrated. We also show that PBTI is explained only by trapping in stress induced defects and not by trapping in pre-existing ones. Dependence on oxide field, temperature activation and recovery of PBTI are also investigated and modeled.
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2010;
[Show abstract][Hide abstract] ABSTRACT: We report an experimental study of the defects induced by the TiN metal gate. N-induced defects are evidenced and energy profile through the Si band gap is measured by original spectroscopic charge pumping measurements. The density of defects is then correlated to the electron mobility degradation and compared to a theoretical model.
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European; 01/2010
[Show abstract][Hide abstract] ABSTRACT: Bias temperature instabilities (BTI) reliability is investigated in advanced dielectric stacks. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.
[Show abstract][Hide abstract] ABSTRACT: This paper provides a systematic study of mobility performance and Bias Temperature Instabilities (BTI) reliability in advanced dielectrics stacks. By studying a large variety of dielectric stacks we clearly demonstrate that mobility performance, interface defects Nit and Negative BTI reliability are strongly correlated. All are affected by nitrogen species N which is clearly identified as the main mobility killer when it reaches unintentionally the Si interface during the deposition of nitrided gates or the nitridation steps.
[Show abstract][Hide abstract] ABSTRACT: The origin of parasitic leakage that occurs in some GeOI pMOSFETs has been investigated and located at the Ge-buried oxide (BOX) interface. Silicon passivation of that interface was found to be effective in reducing this current. An optimum thickness of the buried silicon capping is required to reduce the parasitic leakage current while preserving Ge-like back channel transport properties.
[Show abstract][Hide abstract] ABSTRACT: The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard gate stack or an advanced high-κ/metal gate stack. It is demonstrated that strained devices exhibit significantly reduced leakage currents (up to −90% at Eox = 11 MV/cm for σtensile = 2.5 GPa). This specific effect is used to extract the conduction band offset ΔEc induced by strain and is shown to be accurate enough to monitor stress in MOSFETs. This new technique is much less sensitive to gate oxide defects than the method based on the threshold voltage shift ΔVT. This accurate experimental extraction allowed us to pick out realistic values for the deformation potentials in silicon (Ξu = 8.5 eV and Ξd = −5.2 eV), among the published values.