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2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011; 01/2011
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Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011; 01/2011
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Embedded Systems Letters. 01/2010; 2:53-57.
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11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010; 01/2010
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8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), Grenoble, France, 26-28 July 2010; 01/2010
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01/2010; Springer., ISBN: 978-90-481-3630-8
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IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010; 01/2010
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[show abstract]
[hide abstract]
ABSTRACT: Modelling at the Electronic System Level (ESL) is the established approach of the major System-on-chip (SoC) companies. While
in the past ESL design covered design methodologies only, today also verification and debugging is included. To improve the
verification process, testbench automation has been introduced highlighted as constraint-based random simulation. In SystemC
–the de facto standard modelling language for ESL– constraint-based random simulation is available through the SystemC Verification
(SCV) library. However, the underlying constraint-solver is based on Binary Decision Diagrams (BDDs) and hence suffers from
memory problems. In this chapter, we propose the integration of new techniques for stimuli generation based on Satisfiability
Modulo Theories (SMT). Since SMT solvers are designed to determine a single satisfying solution only, several strategies are
proposed forcing the solver to generate more than one stimuli from different parts of the search space. Experiments demonstrate
the advantage of the proposed approach and the developed strategies in comparison to the original BDD-based method.
KeywordsConstraint-based random simulation-SAT modulo theories-SystemC verification library
12/2009: pages 227-244;
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Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009; 01/2009
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Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009; 01/2009
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2009; 28:703-715.
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ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan; 01/2009
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10th International Workshop on Microprocessor Test and Verification, MTV 2009, Austin, Texas, USA, 7-9 December 2009; 01/2009
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Multiple-Valued Logic and Soft Computing. 01/2009; 15:283-300.
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Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009; 01/2009
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VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009; 01/2009
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Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009; 01/2009
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[show abstract]
[hide abstract]
ABSTRACT: Constraint-based random simulation is state-of-the-art in verification of multi-million gate industrial designs. This method
is based on stimulus generation by constraint solving. The resulting stimuli will particularly cover corner case test scenarios
which are usually hard to identify manually by the verification engineer. Consequently, constraint-based random simulation
will catch corner case bugs that would remain undetected otherwise. Therefore, the quality of design verification is increased
significantly. However, in the process of constraint specification for a specific test scenario, the verification engineer
is faced with the problem of over-constraining, i.e.the overall constraint specified for a test scenario has no solution.
In this case the root cause of the contradiction has to be identified and resolved. Given the complexity of constraints used
to describe test scenarios, this can be a very time-consuming process.
In this chapter we propose a fully automated contradiction analysis method. Our method determines all “nonrelevant” constraints
and computes all reasons that lead to the over-constraining. Thus, we pinpoint the verification engineer to exactly the sets
of constraints that have to be considered to resolve the over-constraining. Experiments have been conducted in a real-life
SystemC-based verification environment at AMD Dresden Design Center. They demonstrate a significant reduction of the constraint
contradiction debug time.
12/2008: pages 273-290;
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2008; 27:1305-1314.
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Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008; 01/2008
