D.S. Yu

National Chiao Tung University, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (29)39.52 Total impact

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    ABSTRACT: High mobility channel materials such as Ge and compound semiconductors (CS) show promise for future generation MOSFETs. The challenge is to integrate these materials with a Si substrate and create good interfaces in the devices. Here we show dislocation-free CSOI and Ge-on-insulator (GOI) devices with good characteristics. The InAlAs/InGaAs/InAlAs-OI on Si MESFETs shows a mobility of 8100cm2/Vs. To reduce the leakage current an Al2O3/InGaAs MOSFET was fabricated. Good 451cm2/Vs mobility was obtained, higher than the 340cm2/Vs of GOI MOSFETs. However the marginally better mobility than GOI and 18X lower mobility than MESFETs indicate that the soft phonon scattering, high-κ interface scattering and process variations are challenges for CS MOSFETs. In contrast, the GOI CMOS provides a simpler process and significantly higher electron and hole mobilities than its Si counterparts.
    Materials Science in Semiconductor Processing 08/2006; DOI:10.1016/j.mssp.2006.08.066 · 1.76 Impact Factor
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    ABSTRACT: We demonstrate a dislocation-free InAlAs/InGaAs/InAlAs-on-Insulator (IIIVOI) HEMT on a Si substrate, which has a high drain current and 8,100 cm2/Vs mobility. To reduce the Schottky gate leakage current in the device, a high-¿ Al2O3/InGaAs gate stack was used. By using this structure the gate leakage current was lower than that for a SiO2/Si MOSFET at the same equivalent-oxide-thickness (EOT), and the measured 451 cm2/Vs effective mobility was 2.5X higher.
    Device Research Conference, 2006 64th; 07/2006
  • D. S. Yu · H. L. Kao · A. Chin · S. P. McAlister
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    ABSTRACT: The performance of field-effect transistors may be improved by increasing the channel mobility. Strained Si can accomplish this but Ge is another option. Here we show data for germanium-on-insulator (GOI) devices and also describe the simple bonding process which was used in the device fabrication. The GOI devices show better mobilities than their Si counterparts. We also show data for some metal-gate/high-κ dielectric devices on a GOI layer fabricated on a processed Si wafer. Here the GOI structure and processing does not alter the underlying Si devices and yet gives devices whose mobilities exceed those of Si devices. Simulations support the view that the improved performance results from the mobility enhancement and that the performance should also hold for submicron devices.
    Journal of Vacuum Science & Technology A Vacuum Surfaces and Films 05/2006; 24(3). DOI:10.1116/1.2167978 · 2.14 Impact Factor
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    ABSTRACT: We have fabricated the fully silicided Ir<sub>x</sub>Si-gated p-MOSFETs on HfAlON gate dielectric with 1.7-nm equivalent oxide thickness. After 950°C rapid thermal annealing, the fully Ir<sub>x</sub>Si/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm<sup>2</sup>/V·s, and the advantage of being process compatible to the current VLSI fabrication line.
    IEEE Electron Device Letters 03/2006; 27(2-27):90 - 92. DOI:10.1109/LED.2005.862687 · 3.02 Impact Factor
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    ABSTRACT: To improve trapping using deeper well AlGaN (chi=3.8eV), lower voltage drop in high-K AlLaO<sub>3</sub> barrier (k=23 ), and smaller erase current by large DeltaE<sub>C</sub> of AlLaO<sub>3</sub>/TaN, the SiO<sub>2</sub>/AlGaN/AlLaO<sub>3</sub>/TaN devices show good 85degC memory integrity of low plusmn10V 1ms P/E, large 3.9V initial DeltaV<sub>th</sub> and 2.4V extrapolated 10-year retention. A fast 100mus P/E of plusmn11V still gives 3.0V initial DeltaV<sub>th </sub> and 1.6V 10-year retention
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: Metallic diffusion through high-K HfO<sub>2</sub>, caused by high temperature metal-nitride decomposition, was reduced by using robust HfAlON. Useful dual effective work-function (phi<sub>m,eff</sub>) of 4.25 and 5.15 eV are obtained in TaTb<sub>0.2</sub>N/HflON and Ir/HfAlON at 1.7 nm EOT. Good dual phi<sub>m,eff</sub> of 4.15 and 4.9 eV are also obtained in Yb<sub>x</sub>Si/HfAlON and Ir<sub>x</sub>Si/HfAlON FUSI-gates by reduced metal diffusion at lower temperature
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: We have used process and device simulation tools (T-Supreme and Medici) to analyze the measured DC characteristics of Ge-on-insulator (GOI) MOSFETs. The GOI devices have higher drive current than do their Si counterparts, due to the smaller effective mass (m*) and smaller Ge energy bandgap - however this also causes a larger off-state I<sub>ds</sub> leakage current. The simulations predict that the GOI MOSFETs have better RF gain and noise performance compared with Si devices. This is important for high speed operation as down-scaling continues.
    Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
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    ABSTRACT: We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-κ/Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 μm CMOSFETs. The devices used IrO<sub>2</sub>--IrO<sub>2</sub>-Hf dual gates and a high-κ LaAlO<sub>3</sub> gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-κ/GOI p-and n-MOSFETs displayed threshold voltage (V<sub>t</sub>) shifts of 30 and 21 mV after 10 MV/cm, 85°C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-κ-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.
    IEEE Electron Device Letters 07/2005; DOI:10.1109/LED.2005.848130 · 3.02 Impact Factor
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    ABSTRACT: We have studied bias-temperature instability (BTI) on fully nickel-silicided (NiSi) and germanided (NiGe) gates on high- n metal oxide semiconductor field effect transistors (MOSFETs) and pMOSFETs, respectively. At an equivalent oxide thickness of , the pMOSFETs and nMOSFETs have a comparable threshold voltage change of and at and stress for . This result is different from the more severe negative BTI (NBTI) degradation measured in oxynitride pMOSFET than positive BTI (PBTI) in nMOSFET. The extrapolated maximum voltage for ’ lifetime is 1.16 and from complementary MOSFETs (CMOSFETs) that can barely meet the required operation with 10% safety margin. Further improvement is still required because the oxynitride CMOSFETs have higher ’ lifetime operation voltages of 2.48 and for PBTI and NBTI, respectively.
    05/2005; 152(6):G452-G455. DOI:10.1149/1.1901104
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    ABSTRACT: We demonstrate three-dimensional (3-D) self-aligned [IrO<sub>2</sub>-IrO<sub>2</sub>-Hf]-LaAlO<sub>3</sub>-Ge-on-Insulator (GOI) CMOS FETs above 0.18-μm Si CMOS FETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO<sub>2</sub>-LaAlO<sub>3</sub>-GOI p-MOSFETs and IrO<sub>2</sub>-Hf-LaAlO<sub>3</sub>-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm<sup>2</sup>/Vs respectively, without depredating the underneath 0.18-μm Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.
    IEEE Electron Device Letters 03/2005; 26(2-26):118 - 120. DOI:10.1109/LED.2004.841861 · 3.02 Impact Factor
  • IEEE Electron Device Letters 02/2005; 26(2):118-120. · 3.02 Impact Factor
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    ABSTRACT: For the first time, we demonstrate 3D integration of self-aligned IrO<sub>2</sub>(Hf)/LaAlO<sub>3</sub>/GOI CMOSFETs above 0.18 μm Si CMOSFETs. At EOT=1.4nm, the novel IrO<sub>2</sub>(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO<sub>3</sub>/Si devices have high electron and hole mobilities of 203 and 67 cm<sup>2</sup>/Vs. On the 3D structure the LaAlO<sub>3</sub>/ GOI shows even higher 389 and 234 cm<sup>2</sup>/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
  • Journal of The Electrochemical Society 01/2005; 152(8). DOI:10.1149/1.1949088 · 2.86 Impact Factor
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    ABSTRACT: We propose and demonstrate a new VLSI structure using high performance metal-gate/high-K MOSFETs and high-Q RF passive devices on Ge-on-insulator (GOI) platform. In additional to high RF performance passive devices on insulating Si formed by ion implantation, the metal-gate/(La)AlO<sub>3</sub>/GOI MOSFETs have 1.7-2.0X improved electron and hole mobility with the merits of minimizing interfacial reaction high-K crystallization, Fermi-level pinning, and impurity diffusion due to low thermal budget of 500° C RTA.
    Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004
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    ABSTRACT: We have integrated the low work function NiSi:Hf gate on high-κ LaAlO<sub>3</sub> and on smart-cut Ge-on-insulator (SC-GOI) n-MOSFETs. At 1.4-nm equivalent oxide thickness, the NiSi:Hf-LaAlO<sub>3</sub>/SC-GOI n-MOSFET has comparable gate leakage current with the control Al gate on LaAlO<sub>3</sub>-Si MOSFETs that is ∼5 orders of magnitude lower than SiO<sub>2</sub>. In addition, the LaAlO<sub>3</sub>/SC-GOI n-MOSFET with a metal-like fully NiSi:Hf gate has high peak electron mobility of 398 cm<sup>2</sup>/Vs and 1.7 times higher than LaAlO<sub>3</sub>-Si devices.
    IEEE Electron Device Letters 09/2004; 25(8-25):559 - 561. DOI:10.1109/LED.2004.832527 · 3.02 Impact Factor
  • IEEE Electron Device Letters 08/2004; 25(8):559-561. · 3.02 Impact Factor
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    ABSTRACT: The main challenges for metal-gate/high-k CMOS are to find dual workfunction gates and robust high-k dielectrics. The low workfunction metal-gate for n-MOS is especially difficult since it reacts with oxygen rapidly and is hard to form a silicide or nitride. We have successfully developed 4.2 and 4.3 eV low workfunction NiSi:Hf and NiTiSi gates that were integrated onto SiO<sub>2</sub>/Si, novel high-k LaAlO<sub>3</sub>/Si and LaAlO<sub>3</sub>/GOI n-MOSFETs. The Hf or TiSi is for low workfunction control and the NiSi is for low resistivity.
    Device Research Conference, 2004. 62nd DRC. Conference Digest [Late News Papers volume included]; 07/2004
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    ABSTRACT: Using optimized ion implantation, we have fabricated high performance 2-pole and 3-pole CPW filters on Si substrates at ∼30 GHz, with very narrow 1.0 (3.1%) GHz and 0.75 (2.5%) GHz pass-band as well as small insertion loss. Microstrip filters on Si show small 3.2 dB loss at 27 GHz, which has smaller size than CPW case without the large coplanar ground planes. In contrast, the nonimplanted filters failed due to the high substrate loss.
    Microwave Symposium Digest, 2004 IEEE MTT-S International; 07/2004
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    ABSTRACT: High-κ Al<sub>2</sub>O<sub>3</sub>/Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the Al<sub>2</sub>O<sub>3</sub>-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with Al<sub>2</sub>O<sub>3</sub>-Si MOSFETs. Additionally, Al<sub>2</sub>O<sub>3</sub>-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than Al<sub>2</sub>O<sub>3</sub>-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500°C rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-κ to minimize interfacial reactions and crystallization of the high-κ material, and oxygen penetration in high-κ MOSFETs.
    IEEE Electron Device Letters 03/2004; 25(3):138-140. DOI:10.1109/LED.2004.824249 · 3.02 Impact Factor
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    ABSTRACT: We demonstrate for the first time fully silicided NiSi (4.55 eV) and germanided NiGe (5.2 eV) dual gates on 1.9 nm-SiO<sub>2</sub>/Si and Al<sub>2</sub>O<sub>3</sub>/Ge-on-insulator (GOI) MOSFETs (EOT= 1.7 nm). In additional to the comparable gate current and time-to-breakdown with Al gate C-MOSFETs, the fully NiSi and NiGe gates on SiO<sub>2</sub>/Si show mobility close to universal mobility while on Al<sub>2</sub>O<sub>3</sub>/GOI show ∼2.0× higher peak electron and hole mobility than Al on Al<sub>2</sub>O<sub>3</sub>/Si, with the special advantage of NiSi and NiGe being compatible to current VLSI process lines.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004