ABSTRACT: As the device geometry continued to be scaled toward deep sub-micron, high dose ion implantation was essential in the source/drain engineering for semiconductor device fabrication. However, carbonized photoresist residuals became a critical issue in the photoresist stripping step of high dose ion implantation process. In order to remove photoresist residuals effectively and completely, a fluorine-based gas such as CF<sub>4</sub> was widely used in photoresist ashing applications. A non-optimized CF<sub>4</sub> ashing recipe would cause fluorine penetration into the gate oxide and affect device parameters. In this work, ashing recipes with different CF<sub>4</sub> plasma processing times were used in the source/drain photoresist stripping process to evaluate its influence. Results of this experiment showed that longer CF<sub>4</sub> plasma processing time gave rise to more gate oxide thickness, higher threshold voltage, negative shift of flatband voltage, good immunity to hot carrier injection (HCI) stress and improved negative bias threshold instability (NBTI). In addition, oxide integrity degradation in charge-to-breakdown (Q<sub>bd</sub>) was observed.
Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the; 02/2002