[Show abstract][Hide abstract] ABSTRACT: There is an increasing concern involving the security, trust, and reliability of the hardware underlying the information systems on which modern society is reliant for mission-critical and safety-critical functions. Secure, trustworthy and reliable hardware components, and platforms and supply chains are vital to all domains, including financial, healthcare, transportation, energy, and the national defense. Traditionally, authenticity, integrity, and confidentiality of information were being protected with security protocols in software with the underlying hardware assumed to be secure, trustworthy, and reliable. However, this assumption is no longer true with an increasing number of attacks being reported on the hardware root of trust. Whereas security, trust, and reliability risks are better understood in software, understanding and addressing threats to the hardware root of trust are a critical emerging challenge and the focus of this special issue.
Emerging Topics in Computing, IEEE Transactions on. 01/2014; 2(1):2-3.
[Show abstract][Hide abstract] ABSTRACT: We propose a novel harvesting technology to inconspicuously transduce mechanical energy from human foot-strikes and explore its configuration and control toward optimized energy output. Dielectric elastomers (DEs) are high-energy density, soft material that electrostatically transduce mechanical energy. These properties enable increased energy-transduction efficiency without sacrificing user comfort, if configured and controlled properly. We expose key statistical properties of human gait, which show that an array of miniaturized harvesters across the foot-sole will improve energy output. Further, the gait properties naturally yield a closed-loop control strategy to individually control harvesters in the array in a manner that maximizes net energy output. We propose statistical techniques that guide the configuration and control of the harvester array, and evaluate system behavior from detailed analytical and empirical models of DE behavior. System evaluations based on experimentally collected foot pressure data sets show that the proposed system can achieve up to 120 mJ per foot-strike.
[Show abstract][Hide abstract] ABSTRACT: A physical unclonable function (PUF) is an integrated circuit (IC) that serves as a hardware security primitive due to its complexity and the unpredictability between its outputs and the applied inputs. PUFs have received a great deal of research interest and significant commercial activity. Public PUFs (PPUFs) address the crucial PUF limitation of being a secret-key technology. To some extent, the first generation of PPUFs are similar to SIMulation Possible, but Laborious (SIMPL) systems and one-time hardware pads, and employ the time gap between direct execution and simulation. The second PPUF generation employs both process variation and device aging which results in matched devices that are excessively difficult to replicate. The third generation leaves the analog domain and employs reconfigurability and device aging to produce digital PPUFs. We survey representative PPUF architectures, related public protocols and trusted information flows, and related testing issues. We conclude by identifying the most important, challenging, and open PPUF-related problems.
Proceedings of the IEEE 01/2014; 102(8):1142-1156. · 6.91 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Hardware Trojans (HTs) have become a major concern in the modern integrated circuit (IC) industry, especially with the fast growth in IC outsourcing. HT detection and diagnosis are challenging due to the huge number of gates in modern IC designs and the high cost of testing. We propose a scalable and efficient HT detection and diagnosis scheme based on segmentation and consistency analysis of gate-level properties. In addition, we employ a self-consistency-based approach, where we conduct variable elimination and create subsegments from a fixed set of power measurements of the entire IC to minimize the number of power measurements. We evaluate our HT detection and diagnosis schemes on a set of ISCAS and ITC benchmarks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2014; 22(9):1845-1853. · 1.22 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Although mobile health monitoring where mobile sensors continuously gather, process, and update sensor readings (e.g. vital signals) from patient's sensors is emerging, little effort has been investigated in an energy-efficient management of sensor information gathering and processing. Mobile health monitoring with the focus of energy consumption may instead be holistically analyzed and systematically designed as a global solution to optimization subproblems. We propose a distributed and energy-saving mobile health platform, called mHealthMon where mobile users publish/access sensor data via a cloud computing-based distributed P2P overlay network. The key objective is to satisfy the mobile health monitoring application's quality of service requirements by modeling each subsystem: mobile clients with medical sensors, wireless network medium, and distributed cloud services. By simulations based on experimental data, we present the proposed system can achieve up to 10.1 times more energy-efficient and 20.2 times faster compared to a standalone mobile health monitoring application, in various mobile health monitoring scenarios applying a realistic mobility model.
Engineering in Medicine and Biology Society (EMBC), 2013 35th Annual International Conference of the IEEE; 01/2013
[Show abstract][Hide abstract] ABSTRACT: We have developed a new security hardware primitive named digital bimodal function (DBF) that enables ultra low energy security protocols. DBF allows the computation of legitimate communicating sides to be compact and low-energy while it requires any attacker exponential computational effort and energy expense. Our new approach is competitive with the energy efficiency of traditional security key cryptographic security technique (e.g., AES) while more than three orders of magnitude more energy efficient than RSA. The implementation is demonstrated using the Xilinx FPGA platform.
Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: As sensor equipped wearable systems enter the mainstream, system longevity and power-efficiency issues hamper large scale and long-term deployment, despite substantial foreseeable benefits. As power and energy efficient design, sampling, processing and communication techniques emerge to counter these issues, researchers are beginning to look on wearable energy harvesting systems as an effective counterpart solution. In this paper, we propose a novel harvesting technology to inconspicuously transduce mechanical energy from human foot-strikes and power low-power wearable systems in a self-sustaining manner. Dielectric Elastomers (DEs) are high-energy density electrostatic transducers that can transduce significant levels of energy from a user while appearing near-transparent to her, if configured and controlled properly. Towards this end, we propose DE-based harvester configuration that capitalizes on properties of human gait to enhance transduction efficiency, and further leverage these properties in an adaptive control algorithm to optimize the net energy produced by the system. We evaluate system performance from detailed analytical and empirical models of DE transduction behavior, and apply our control algorithm to the modeled DEs under experimentally collected foot pressure datasets from multiple subjects. Our evaluations show that the proposed system can achieve up to 120mJ per foot-strike, enough to power a variety of low-power wearable devices and systems.
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: We propose a novel strategy for energy-efficient operation of wireless monitoring devices under the premise that medical experts are primarily interested in atypical observations - For epilepsy monitoring, EEG data is most valuable at epileptic activity onset. Or, a gait-stability monitoring application is most interested in unusual footsteps. Observations are atypical if application-specific medical metrics and biosignal features are statistical outliers. Our strategy admits energy-efficient early-detection of such observations, leading to: (i) an increase in medical information quality by sampling aggressively over semantically important behaviors, and (ii) a savings in energy by precluding communication of typical measurements. From experimentally collected plantar pressure datasets, we show that this can yield up to a 62% improvement in gait-stability metric evaluation for atypical footsteps and a 10% energy cost reduction compared to a recently proposed non-adaptive compressive sensing technique.
[Show abstract][Hide abstract] ABSTRACT: Hardware metering, the extraction of unique and persistent identifiers (IDs), is a crucial process for numerous integrated circuit (IC) intellectual property protection tasks. The currently known hardware metering approaches, however, are subject to alternations due to device aging, since they employ unstable manifestational IC properties. We, on the other hand, have developed the first robust hardware metering approach by using physical-level gate proprieties for ID generation. By using effective channel length, which is resilient to aging, and threshold voltage, which is essentially independent across gates and suitable for calculating the uniqueness of the IDs, we overcome the limitations of the existing approaches. Also, despite the increase in threshold voltage that occurs with aging, the original threshold voltage value can be extracted through intentional IC aging. Our ID generation procedure first employs two types of side channels, namely switching power and leakage power, to extract metering results for each gate. Next, we show that localized delay measurements alone are sufficient for accurate characterization of large sets of gates. Finally, by using threshold voltage for ID creation, we are able to obtain low probabilities of coincidence between legitimate and pirated ICs. The application of the approach to a set of benchmarks quantitatively establishes the effectiveness of the new hardware metering approach.
IEEE Transactions on Information Forensics and Security 01/2013; 8(11):1722-1730. · 1.90 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Recent advances in the scope of wearable devices and networks make body area sensor networks (BASNs) an extremely attractive tool to the fields of mobile and tele-health, owing to the range of medical applications they can serve and the diagnostic richness of patient data they can offer. However, for BASNs to achieve true ubiquity, they must be scalable in their support of automated patient data collection, making usability and reliability key considerations. Its designers must wrestle with the tradeoff between usability, hindered by device intrusiveness into the behaviors it measures, and lifetime, enhanced by large power supplies and expensive, sturdy components. Furthermore, the validity and reliability of the collected data are paramount. In this paper, we consider these issues in the context of localized multi-sensory wearable networks and present a method to generate low-power sampling schedules that are resilient to sensor faults while achieving high diagnostic fidelity. We jointly formulate this as a power-constrained sampling problem wherein the number of sensors sampled per epoch are limited, and, a fault tolerant scheduling problem wherein the sampling scheme offers enough redundancy to endure up to a predefined number of sensor faults while maintaining diagnostic accuracy. This formulation is based on, 1) the localized scope of BASNs that engenders strong spatio-temporal interactions in the samples, and, 2) the periodic nature of human behaviors measured. We present our algorithm in the context of gait diagnostics derived from a foot plantar pressure measurement platform and illustrate its performance based on real datasets collected by it.
Emerging and Selected Topics in Circuits and Systems, IEEE Journal on. 01/2013; 3(1):86-95.
[Show abstract][Hide abstract] ABSTRACT: Random Number Generator (RNG) plays an essential role in many sensor network systems and applications, such as security and robust communication. We have developed the first digital hardware random number generator (DHRNG). DHRNG has a small footprint and requires ultra-low energy. It uses a new recursive structure that directly targets efficient FPGA implementation. The core idea is to place or extract random values in FPGA configuration bits and randomly connect the building blocks. We present our architecture, introduce accompanying protocols for secure public key communication, and adopt the NIST randomness test on the DHRNG's output stream.
[Show abstract][Hide abstract] ABSTRACT: The presence of process variation (PV) in deep submicron technologies has become a major concern for energy optimization attempts on FPGAs. We develop a negative bias temperature instability (NBTI) aging-based post-silicon leakage energy optimization scheme that stresses the components that are not used or are off the critical paths to reduce the total leakage energy consumption. Furthermore, we obtain the input vectors for aging by formulating the aging objectives into a satisfiability (SAT) problem. We synthesize the low energy design on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks.
Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: Accurate thermal knowledge is essential for achieving ultra low power in deep sub-micron CMOS technology, as it affects gate speed linearly and leakage exponentially. We propose a temperature-aware synthesis technique that efficiently utilizes input vector control (IVC), dual-threshold voltage gate sizing (GS) and pin reordering (PR) for performing simultaneous delay and leakage power optimization. To the best of our knowledge, we are the first to consider these techniques in a synergistic fashion with thermal knowledge. We evaluate our approach by showing improvements over each method when considered in isolation and in conjunction. We also study the impact of employing considered techniques with/without accurate thermal knowledge. We ran simulations on synthesized ISCAS-85 and ITC-99 circuits on a 45 nm cell library while conforming to an industrial design flow. Leakage power improvements of up to 4.54X (2.14X avg.) were achieved when applying thermal knowledge over equivalent methods that do not.
Computer Design (ICCD), 2013 IEEE 31st International Conference on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: We introduce a novel gate sizing approach that considers both the gate switching activity (SA) and gate input vector control leakage (IVC). We first extract SA using simulation and find promising input vectors. Next, in an iterative framework, we interchangeably conduct gate sizing and refining the IVC. As dictated by the new objective function, our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. We evaluate our approach on standard benchmarks in 45 nm technology, showing promising improvement, achieving up to 62% (29% avg.) energy savings compared to the traditional objective function.
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: Near-Threshold Computing (NTC) shows potential to provide significant energy efficiency improvements as it alleviates the impact of leakage in modern deep sub-micron CMOS technology. As the gap between supply and threshold voltage shrink, however, the energy efficiency gains come at the cost of device performance variability. Thus, adopting near-threshold in modern CAD flows requires careful consideration when addressing commonly targeted objectives. We propose a process variation-aware near-threshold voltage (PV-Nvt) gate sizing framework for minimizing power subject to performance yield constraints. We evaluate our approach using an industrial-flow on a set of modern benchmarks. Our results show our method achieves significant improvement in leakage power, while meeting performance yield targets, over a state-of-the-art method that does not consider near-threshold computing.
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: Hardware-based physically unclonable functions (PUFs) are elegant security primitives that leverage process variation inherent in modern integrated circuits. Recently proposed matched public PUFs (mPPUFs) use a combination of coordinated device aging and gate disabling to create two PUFs that securely realize identical input-output mappings. However, mPPUFs of any reasonable size allow for protocols between only a very limited number of parties. We propose quantization of possible delay values to enable matching of an unbounded number of arbitrary PPUF instances, improving stability in the presence of fluctuations in temperature or supply voltage while maintaining resiliency against a wide number of attacks.
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on; 01/2012
[Show abstract][Hide abstract] ABSTRACT: We present a new method for spatiotemporal assignment and scheduling of energy harvesters on a medical shoe tasked with measuring gait diagnostics. While prior work exists on the application of dielectric elastomers (DEs) for energy scavenging on shoes, current literature does not address the issues of placement and timing of these harvesters, nor does it address integration into existing sensing systems. We solve these issues and present a self-sustaining medical shoe that harvests energy from human ambulation while simultaneously measuring gait characteristics most relevant to medical diagnosis.
[Show abstract][Hide abstract] ABSTRACT: In this paper we present the use of Benign Hardware Trojans (BHT) as a security measure for an embedded system with a software component and a hardware execution environment. Based on delay logic, process variation, and selective transistor aging, the BHT can be incorporated into an embedded system for the software and the hardware components to authenticate each other before functional execution. We will demonstrate an implementation of such a BHT within an embedded system on a Xilinx Spartan-6 FPGA platform. Using the same platform we will also show that the BHT security measurement has a low to modest amount of performance overhead basing on the test results from a variety of synthetic and real world benchmarks.
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on; 01/2012
[Show abstract][Hide abstract] ABSTRACT: Parasitic energy scavenging from human-generated vibrations with piezoelectric materials has long been studied in contrast to electromagnetic or conventional electrostatic transducers. Dielectric Elastomers (DEs) are now gaining notice as low-cost electrostatic transducers with high energy densities. However, their transduction mechanism is more intricate. DE Generators (DEGs) are functionally variable capacitors, which require fine-grained control of their charging cycles in order to maximize the energy transduced. Based on a detailed DEG model that incorporates an effective method to time the charge cycles, we contrast the energy scavenged from shoe strikes by DEGs that are virtually embedded into the shoe sole, to similar piezoelectric generators. This comparison for a plantar pressure dataset of a walking subject demonstrates a multiple order-of-magnitude improvement in harvested energy.
[Show abstract][Hide abstract] ABSTRACT: This paper proposes a novel minimal test point insertion methodology that provisions a provably complete detection of hardware Trojans by noninvasive timing characterization. The objective of test point insertion is to break the reconvergent paths so that target routes for Trojan delay testing are specifically observed. We create a satisfiability-based input vector selection for sensitizing and characterizing each single timing path. Evaluations on benchmark circuits demonstrate that the test point-based Trojan detection can cover all circuit locations and can detect Trojans accurately with less than 5% performance overhead.
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on; 01/2012