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ABSTRACT: In this study, a simple approach for designing a matrix filter with controlled mean-square sidelobe level is proposed. Two methods are used for designing the matrix filter. In design method 1, the authors minimise the normalised mean-square error between the designed and the desired filter responses in the passband subject to the different normalised mean-square error constraints in the left and right stopbands. In design method 2, the objective function and the constraints in the design method 1 are reversed. By using Lagrange multiplier theory, the optimal solution and the optimal value of the optimisations are given, the equations of finding the optimal Lagrange multipliers are offered. In addition, the optimal matrix lowpass filters with symmetric stopband region and equally sidelobe level are given, the matrix codiagonalisation method is used for improving the design efficiency. Numerical results show that the proposed approach is effective for designing matrix filter and filtering short data records.
IET Signal Processing 07/2011; · 0.56 Impact Factor
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Electron Devices Meeting (IEDM), 2011 IEEE International; 01/2011
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J. Oh,
S.-H. Lee,
K.-S. Min,
J. Huang,
B.G. Min,
B. Sassman,
K. Jeon,
W.-Y. Loh,
J. Barnett,
I. Ok, C.-Y. Kang,
C. Smith,
D.-H. Ko,
P.D. Kirsch,
R. Jammy
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ABSTRACT: We report a comprehensive study of surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS. On a (110) surface, SiGe nMOS demonstrates a higher electron mobility than Si (110) nMOS. The hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <;110> channel direction with appropriate uniaxial channel strain. Results obtained in this work advance the integration technique of high mobility CMOS on a single SiGe (110)<;110> channel orientation to enhance overall performance without the process complexity associated with hybrid channel CMOS approaches.
VLSI Technology (VLSIT), 2010 Symposium on; 07/2010
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J. Huang,
N. Goel,
H. Zhao, C.Y. Kang,
K.S. Min,
G. Bersuker,
S. Oktyabrsky,
C.K. Gaspe,
M.B. Santos,
P. Majhi,
P.D. Kirsch,
H.-H. Tseng,
J.C. Lee,
R. Jammy
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ABSTRACT: The performance and reliability of ZrO<sub>2</sub>/In<sub>0.53</sub>Ga<sub>0.47</sub>As MOSFETs are shown to be improved by simultaneous reduction of dielectric and interface charges. An amorphous (La)AlO<sub>x</sub> interlayer at the ZrO<sub>2</sub>/In<sub>0.53</sub>Ga<sub>0.47</sub>As interface is a key to reduce border traps, interface traps and move ZrO<sub>2</sub> fixed charge away from the In<sub>0.53</sub>Ga<sub>0.47</sub>As. Border traps are reduced ~3x, effective fixed charges are reduced ~3x and interface trap density is reduced ~1.5x. The net effect of the improved stack is 50% normalized I<sub>d</sub> improvement and 75% normalized G<sub>m</sub> improvement. P/NBTI cyclic stress results indicate Al<sub>2</sub>O<sub>3</sub>/ZrO<sub>2</sub> is more reliable than ZrO<sub>2</sub> only. ¿V<sub>th</sub> of the bilayer show excellent repeatability; conversely, ¿V<sub>th</sub> of ZrO<sub>2</sub> shows permanent (not recoverable) interface degradation during relaxation (NBTI stress). La incorporation in Al<sub>2</sub>O<sub>3</sub> increases the ¿-value while providing improved reliability over both the ZrO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub>/ZrO<sub>2</sub> stack.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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S. D. Park,
C. Park,
D. C. Gilmer,
H. K. Park, C. Y. Kang,
K. Y. Lim,
C. Burham,
J. Barnett,
P. D. Kirsch,
H. H. Tseng,
R. Jammy,
G. Y. Yeom
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ABSTRACT: Quadratic voltage coefficient of capacitance (VCC) for ZrO <sub>2</sub>– SiO <sub>2</sub> multilayered dielectric metal-insulator-metal capacitors depends strongly on the stacking sequence of the layered dielectrics. The quadratic VCC of an optimized SiO <sub>2</sub>/ ZrO <sub>2</sub>/ SiO <sub>2</sub> stack and ZrO <sub>2</sub>/ SiO <sub>2</sub>/ ZrO <sub>2</sub> stack were +42 and -1094 ppm / V <sup>2</sup> , respectively, despite the same total SiO <sub>2</sub> and ZrO <sub>2</sub> dielectric thickness in the stack. The observed difference in quadratic VCC depending on dielectric stacking sequence is explained by taking into account both the interface and bulk dielectric responses to the applied voltage.
Applied Physics Letters 08/2009; · 3.84 Impact Factor
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J. Oh,
I. Ok, C.-Y. Kang,
M. Jamil,
S.-H. Lee,
W.-Y. Loh,
J. Huang,
B. Sassman,
L. Smith,
S. Parthasarathy,
B.E. Coss,
W.-H. Choi,
H.-D. Lee,
M. Cho,
S.K. Banerjee,
P. Majhi,
P.D. Kirsch,
H.-H. Tseng,
R. Jammy
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ABSTRACT: We report the results of a systematic study to understand low drive current of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (D<sub>it</sub>) and specific contact resistivity (rho<sub>c</sub>), which are comparable (or symmetric) for both n- and p-MOSFETs. Effective masses of electrons, which populate L valleys are large for conductivity and small for the density of states in conventional (100) [110] channel directions, resulting in low electron mobility and carrier concentration in Ge-based nMOSFETs.
VLSI Technology, 2009 Symposium on; 07/2009
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W.-Y. Loh,
P.Y. Hung,
B.E. Coss,
P. Kalra,
Injo Ok,
G. Smith, C.-Y. Kang,
S.-H. Lee,
J. Oh,
B. Sassman,
P. Majhi,
P. Kirsch,
H.-H. Tseng,
R. Jammy
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ABSTRACT: We have developed a novel dual phase-modulated Ni silicide for Schottky barrier and series resistance reduction in dopant-segregated source/drain (DSS) n-MOSFETs. Using pre-silicide N<sub>2</sub> <sup>+</sup> implant (thereafter N-implant), it is possible to selectively form interfacial epitaxial Si-rich NiSi<sub>2</sub>, reducing electron Schottky barrier(SB) from 0.7 eV to 0.34 eV while maintaining a low resistive bulk NiSi, at the same silicide formation temperature. Dual phase-modulated NiSi shows enhanced thermal stability up to 750degC, low rhos of 26 muOmegacm and SB modulation Deltaphi<sub>Bn</sub> = 0.36 eV (expected 81% reduction in contact resistance R<sub>c</sub>). Saturation g<sub>m</sub> for phase-modulated N-modulated DSS n-FETs shows 32% improvement over control NiSi with 22% reduction in series resistance R<sub>ext</sub>, while still maintaining CMOS integratability.
VLSI Technology, 2009 Symposium on; 07/2009
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S.-H. Lee,
J. Huang,
P. Majhi,
P.D. Kirsch,
B.-G. Min,
C.-S. Park,
J. Oh,
W.-Y. Loh, C.-Y. Kang,
B. Sassman, [......],
S. McCoy,
J. Chen,
B. Wu,
G. Moori,
D. Heh,
C. Young,
G. Bersuker,
H.-H. Tseng,
S.K. Banerjee,
R. Jammy
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ABSTRACT: We have studied key parameters for controlling threshold voltage (V<sub>th</sub>) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the V<sub>th</sub> variation same to Si unlike RTA anneal while still having 2.8times mobility gain. We achieved high performance SiGe pMOSFETs with appropriate V<sub>th</sub> [-0.2~-0.3 V], ~1 nm EOT and superior NBTI [<30 mV] reliability for the integration of SiGe channel for pMOSFETs.
VLSI Technology, 2009 Symposium on; 07/2009
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ABSTRACT: A new hot-carrier injection mechanism that depends on gate bias and body thickness in nanoscale floating-body MOSFETs has been identified using 2-D device simulation and hot-carrier degradation measurements. When gate voltage is sufficiently high and the body thickness is thin, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension (SE), resulting in impact ionization at the SE. Hot-carrier stress with accelerated gate voltage may lead to a huge overestimation of lifetime in nanoscale floating-body MOSFETs.
IEEE Electron Device Letters 02/2009; · 2.85 Impact Factor
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C.Y. Kang,
C.D. Young,
J. Huang,
P. Kirsch,
D. Heh,
P. Sivasubramani,
H.K. Park,
G. Bersuker,
B.H. Lee,
H.S. Choi,
K.T. Lee,
Y.-H. Jeong,
J. Lichtenwalner,
A.I. Kingon,
H.-H. Tseng,
R. Jammy
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ABSTRACT: La-doped HfSiO samples show lower threshold voltage (V<sub>th</sub>) and gate current (I<sub>gate</sub>), which is attributed to dipole formation at the high-k/SiO<sub>2</sub> interface. At low and intermediate field stress, La-doped devices exhibit better immunity to positive bias temperature instability (PBTI) due to their lower charge trapping efficiency than the control HfSiO, which mainly results from a dipole-induced greater barrier offset. However, the primary cause for defect generation at high field stress is attributed to the La atoms in the interfacial SiO<sub>2</sub> layer. By optimizing the technique to incorporate nitrogen into the bottom interface, this high field reliability issue can be minimized while maintaining good device characteristics.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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J. Huang,
P.D. Kirsch,
D. Heh, C.Y. Kang,
G. Bersuker,
M. Hussain,
P. Majhi,
P. Sivasubramani,
D.C. Gilmer,
N. Goel,
M.A. Quevedo-Lopez,
C. Young,
C.S. Park,
C. Park,
P.Y. Hung,
J. Price,
H.R. Harris,
B.H. Lee,
H.-H. Tseng,
R. Jammy
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ABSTRACT: For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V<sub>t</sub>, as well as strongly affects mobility, N<sub>it</sub> and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V<sub>t</sub> tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO<sub>2</sub>) IL. T<sub>inv</sub>=1.15 nm and V<sub>t,lin</sub>=0.31 V was obtained while achieving the following attributes: mobility~70%, N<sub>it</sub> <5times10<sup>10</sup> cm<sup>-2</sup>, DeltaV<sub>t</sub><30 m V within wafer, BTI DeltaV<sub>t</sub> <40 m V at 125degC. By optimizing these gate stack factors, we have developed and demonstrated structures for 22 nm node LOP application.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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ABSTRACT: Bi<sub>5</sub>Nb<sub>3</sub>O<sub>15</sub> (B<sub>5</sub>N<sub>3</sub>) films grown under a low oxygen partial pressure (OP) of 1.7 mtorr showed a high leakage current density of 0.1 A/cm<sup>2</sup> at 1.0 MV/cm. However, the leakage current density decreased with increasing OP to a minimum of 5.8 times 10<sup>-9</sup> A/cm<sup>2</sup> for the film grown under 5.1 mtorr due to the decreased number of oxygen vacancies. This film also showed an improved breakdown field of 2.2 MV/cm and a large capacitance density of 24.9 fF /mum<sup>2</sup>. The electrical properties of the film, however, deteriorated with a further increase in OP, which is probably due to the formation of oxygen interstitial ions. Therefore, superior electrical properties for the B<sub>5</sub>N<sub>3</sub> film can be obtained by careful control of OP.
IEEE Electron Device Letters 10/2008; · 2.85 Impact Factor
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Reliability Physics Symposium, 2008. IRPS 2008. IEEE International; 01/2008
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B.H. Lee,
C.D. Young,
R. Choi,
J.H. Sim,
G. Bersuker, C.Y. Kang,
R. Harris,
G.A. Brown,
K. Matthews,
S.C. Song, [......],
J. Peterson,
P. Kirsh,
H.-J. Li,
J. Gutt,
M. Gardner,
H.R. Huff,
P. Zeitzoff,
R.W. Murto,
L. Larson,
C. Ramiller
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ABSTRACT: Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V<sub>th</sub> instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO<sub>2</sub> devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
