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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/1996; 15:493-505.
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/1995; 14:493-502.
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Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994, San Jose, California, USA, November 6-10, 1994; 01/1994
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ABSTRACT: This paper presents a strategy for testing all DC performance of Nyquist data converters including offset error, full scale gain error, integral nonlinearity, and differential nonlinearity. In contrast to previous testing strategies based on linear models that require accurate measurements of circuit performance, our strategy uses a simpler measurement to verify that a circuit performance parameter falls within certain detection thresholds in the presence of measurement noise. Using the proposed strategy, we can evaluate tradeoffs between test set size, test coverage, detection thresholds, measurement noise, chip performance, and estimated yield. Our results support the obvious that smaller measurement noise, stricter detection thresholds, and lower chip performance would require smaller test set and reduce test time. Stricter detection thresholds, on the other hand, would decrease estimated yield. 1 Introduction Data converters are commodity products, yet their testing is very expen...
10/1993;
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ABSTRACT: In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit. In this paper, we present a methodology for analog system verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster.
Design Automation, 1993. 30th Conference on; 07/1993
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ABSTRACT: In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit. In this paper, we present a methodology for analog system verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster. 1 Introduction We have proposed a constraint-driven, top-down design methodology for mixed-mode systems[1] that is supported by analog design tools. An integral part of such methodology is the complete verification of the synthesized circuit in the presence of parasitics due to routing, supply variations, and coupling. Because parasitics degrade analog system performance, it is crucial to verify by simulation as completely as possible the circuit functionality in the presence of these second order effects. Existing design methodologies, manual or automatic [2, 3,...
04/1993;
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ABSTRACT: In this paper a "direct" noise analysis approach for mixedmode systems is presented with experimental results compared with results from the traditional Monte Carlo approach. The direct approach computes noise effects by performing arithmetic on moments of distribution functions that characterize electronic noise. One key advantage of this approach is its ability to compute low error probabilities. From experimental results, it is shown that very low order moments, such as second order, are sufficient for a good estimate of noise effects. 1 Introduction The simulation of mixed analog and digital systems is crucial in system verification as more analog and digital circuits are integrated on the same integrated circuit in data acquisition, automotive, or disk drive electronics applications. For these systems, there is a trend to reduce system power consumption by reducing the supply voltage or minimizing parasitic capacitances. One of the fundamental limit to these power reduction tech...
10/1992;