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ABSTRACT: This paper presents an on-chip characterization method for random variation in minimum sized devices in nanometer technologies, using a sense amplifier-based test circuit. Instead of analog current measurements required in conventional techniques, the presented circuit operates using digital voltage measurements. Simulations of the test structure using predictive 70 nm and hardware based 0.13 mum CMOS technologies show good accuracy (error ~5%-10%) in the prediction of random variation even in the presence of systematic variations. A test chip is fabricated in 0.13 mum bulk CMOS technology and measured to demonstrate the operation of the test structure.
IEEE Journal of Solid-State Circuits 10/2008; · 3.23 Impact Factor
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ABSTRACT: Coherent phonon spectroscopy of a high-quality InN epitaxial layer is carried out using time-resolved second-harmonic generation. A coherent longitudinal optical phonon and plasmon coupling mode only at 447 cm <sup>-1</sup> can be resolved in the spectrum. Its frequency shows no dependence on the photoinjected carrier density up to 1.5×10<sup>19</sup> cm <sup>-3</sup> . This phenomenon is attributed to the hybridization of a coherent A<sub>1</sub>( LO ) phonon with the intrinsic cold plasma accumulated in the near-surface region of InN, where the plasma density could reach on the order of 10<sup>20</sup> cm <sup>-3</sup> , much higher than the bulk carrier concentration 1×10<sup>18</sup> cm <sup>-3</sup> determined by Hall effect measurement.
Applied Physics Letters 12/2004; · 3.84 Impact Factor
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L. Sigal,
J. D. Warnock,
B. W. Curran,
Y. H. Chan,
P. J. Camporese,
M. D. Mayo,
W. V. Huott,
D. R. Knebel, C. T. Chuang,
J. P. Eckhardt,
P. T. Wu
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ABSTRACT: This paper describes the circuit design techniques used for the IBM S/390® Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approaches reduced risk and shortened the design time. The use of timing-driven synthesis/placement methodologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits facilitated the balancing of design time and performance return. The use of robust PLL design, floorplanning, and clock distribution minimized clock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innovations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.
Ibm Journal of Research and Development 08/1997; · 0.72 Impact Factor
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ABSTRACT: In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at $V_{CS}=$ 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations ( $L_{rm eff}$ , <formula formulat-
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ype="inline"> $rm EOT$ , $W_{rm fin}$ , and $H_{rm fin}$ ) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of $mu/sigma$ ratio.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1.22 Impact Factor
