[Show abstract][Hide abstract] ABSTRACT: The goal to achieve grid parity for photovoltaics in the near future is stimulating the development of high efficiency solar cell technologies which has spark off strong activities in silicon heterojunction solar cell development in the recent past leading to a number of high efficiency devices at or beyond 20% efficiency in different laboratories. Heterojunction silicon solar cells show interesting properties which are distinct from those of standard crystalline silicon solar cells due to the combination of thin film and crystalline cell technologies. This paper focuses on device properties of the heterojunction technology (HJT) cell developed at Roth & Rau such as temperature and irradiation dependent performance and cell stability under accelerated stress tests. The results demonstrate an improved energy yield of the Roth & Rau HJT cells that is to be expected under realistic operation conditions.
Energy Procedia 12/2011; 8:153-159. DOI:10.1016/j.egypro.2011.06.117
[Show abstract][Hide abstract] ABSTRACT: Silicon heterojunction solar cells have high open-circuit voltages thanks to excellent passivation of the wafer surfaces by thin intrinsic amorphous silicon (a-Si:H) layers deposited by plasma-enhanced chemical vapor deposition. We show a dramatic improvement in passivation when H2 plasma treatments are used during film deposition. Although the bulk of the a-Si:H layers is slightly more disordered after H2 treatment, the hydrogenation of the wafer/film interface is nevertheless improved with as-deposited layers. Employing H2 treatments, 4 cm2 heterojunction solar cells were produced with industry-compatible processes, yielding open-circuit voltages up to 725 mV and aperture area efficiencies up to 21%.
[Show abstract][Hide abstract] ABSTRACT: This work reports the first results of a new generation plasma-enhanced chemical vapor deposition (PECVD) reactor manufactured by Roth and Rau. This large area parallel plate reactor has been especially designed for the manufacturing of silicon heterojunction solar cells which are made of very thin amorphous silicon films over monocrystalline silicon substrates. Layer thickness uniformity below ± 3 % is reported for both intrinsic and doped layer over a 400 × 400 mm2 area. Moreover, it is shown that the passivation quality is excellent with life-times up to 4.15 ms on n-type FZ silicon substrates. A ± 0.6 % uniformity in open circuit voltage (mean value of 701.4 mV) is achieved over 32 devices having a 4 cm2 area and an average conversion efficiency of 19.5 %.
[Show abstract][Hide abstract] ABSTRACT: Silicon heterojunction technology (Si-HJT) consists of thin amorphous silicon layers on monocrystalline silicon wafers and allows for photovoltaic solar cells with energy-conversion efficiencies above 20%, also at industrial-production level. This article reports how this may be achieved. First, we focus on the surface-passivation mechanism of intrinsic and doped amorphous silicon films in such solar cells, enabling record-high values for the open-circuit voltage. Next, the industrial upscaling in large-area reactors of such film deposition is discussed, including the fabrication of solar cells with energy-conversion efficiencies as high as 21%.
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on; 12/2010
[Show abstract][Hide abstract] ABSTRACT: Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-V<sub>T</sub> regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a theoretical framework about interface state creation rate from Si–H bonds at the Si / Si O <sub>2</sub> interface. It includes three main ways of bond breaking. In the first case, the bond can be broken, thanks to the bond ground state rising with an electrical field. In two other cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows one to physically model the reliability of metal oxide semiconductor field effect transistors, and particularly negative bias temperature instability permanent part, and channel hot carrier to cold carrier damage.
[Show abstract][Hide abstract] ABSTRACT: Channel hot-carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40 nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V<sub>BS</sub>. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V<sub>GS</sub>, V<sub>DS</sub> (V<sub>BS</sub>) conditions as a single I<sub>DS</sub> lifetime dependence is observed with V<sub>GD</sub> > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I<sub>DS</sub>) and multi vibrational excitation (higher I<sub>DS</sub>) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V<sub>BS</sub> = -V<sub>DD</sub> in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V<sub>BS</sub> = -V<sub>DD</sub>/2 for design reliability.
[Show abstract][Hide abstract] ABSTRACT: A general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation.
[Show abstract][Hide abstract] ABSTRACT: The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.
[Show abstract][Hide abstract] ABSTRACT: We have developed a two-dimensional noise model based on a Green's function approach. This model allows slow trap density profiles to be determined. The model was applied in the investigation of low- frequency degradation of MOSFETs stressed by hot- carriers, and the generated slow oxide trap density profiles were deduced. For short stress times, the generated traps were localized in the LDD regions, whereas in the case of long stress times, traps were created in both the LDD and the channel regions.
Ultimate Integration of Silicon, 2008. ULIS 2008. 9th International Conference on; 04/2008
[Show abstract][Hide abstract] ABSTRACT: From extensive set of silicon data presented in this study, we report a new way of understanding and modeling various aspects of NBTI degradation from transistor to product level. This work opens new paths for both relevant process improvements and product optimization.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
[Show abstract][Hide abstract] ABSTRACT: A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes.
IEEE Transactions on Device and Materials Reliability 01/2008; 7(4-7):558 - 570. DOI:10.1109/TDMR.2007.911380 · 1.54 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A novel composite model had been recently introduced to physically explain the mean pMOS threshold voltage shift (V<sub>TP</sub>) induced by NBTI degradation at transistor level in a quantitative way. This model is here extended to include the statistical variations introduced by intrinsic fluctuations. In a second time, the model is extrapolated up to SRAM arrays by analyzing the SRAM bitcell sensitivity to transistor degradation. This approach allows quantitative prediction of NBTI-induced V<sub>MIN</sub> variations and access time T<sub>aa</sub> degradation during burn-in operations. The key findings include (a) demonstration of non-normality of V<sub>TP</sub> shift distribution (b) NBTI contribution to product V<sub>MIN</sub> drift arises from both mean V<sub>TP</sub> drift but also from increased V<sub>TP</sub> dispersion, and (c) V<sub>TP</sub> shift non-normality is smoothed out at product level by time-zero variation of the six transistors of the SRAM bitcell.
[Show abstract][Hide abstract] ABSTRACT: In this work, we confirm that the energy is the driving force of Hot Carrier effects. When the energy is high, the Energy-driven framework allows to retrieve Lucky Electron Model-like equations. But when the energy is lowered, high energy electrons generated by Electron-Electron Scattering become the dominant contribution to the degradation. For even lower energy Multiple Vibrational Excitation mechanism starts taking the lead.
[Show abstract][Hide abstract] ABSTRACT: In this paper, we propose to distinguish the distinct carrier degradation modes as a function of the energy range developing a complete lifetime extrapolation technique down to the low voltage operation. This provides a starting point of a more accurate modeling of CHC effects during product operations. This work shows that CHC effects in nMOSFET consist in three different regimes depending on the gate voltage (Vg). A simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions was detailed for each regime. We also propose an answer to the contradictory debate of the respective contributions of electron-electron scattering (EES) (Rauch et al., 2001) and the multiple vibrational excitation (MVE) (Hess et al., 1999) to CHC effects in the low energy range.
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the; 08/2007
[Show abstract][Hide abstract] ABSTRACT: In this paper, we confirm that the energy is the driving force of hot-carrier effects. In high-energy long-channel case, the energy-driven paradigm allows to retrieve lucky electron model-like equations although the explanations are different. When the energy is lowered, high-energy electrons generated by electron-electron scattering become the dominant contribution to the degradation. Finally, for even lower energy, multiple vibrational excitation mechanism starts taking the lead.
IEEE Transactions on Device and Materials Reliability 07/2007; DOI:10.1109/TDMR.2007.901180 · 1.54 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This work reports for the first time a new positive bias temperature instability (PBTI) degradation mode in n-channel MOSFETs related to the introduction of plasma nitridation process step. The degradation is explained only by interface traps creation, differently to NBTI on p-channel MOSFETs where hole trapping might be dominant
[Show abstract][Hide abstract] ABSTRACT: This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing during a particular condition of degradation. In particular, we gain critical insights into recovery phenomena, which are observed during certain conditions of CHC degradation (Mistry et al., 1991) as well as during NBTI (Rangan, 2003). These findings set the stage for consistent physical models for degradation as well as for design simulation under multiple operating modes
[Show abstract][Hide abstract] ABSTRACT: Practical and accurate Design-in Reliability methodology has been developed for designs on 90-45nm technology to quantitatively assess the degradation due to Hot Carrier and Negative Bias Temperature Instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology illustrating the capabilities of the methodology as well highlighting the impacts of the two degradations modes.