C. Guerin

Université de Toulon, La Garde-près-Toulon, Provence-Alpes-Côte d'Azur, France

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Publications (25)6.47 Total impact

  • [show abstract] [hide abstract]
    ABSTRACT: Thermal gradients, commonly present in our environment (fluid lines, warm fronts, electronics) are sources of energy rarely used today. This paper aims to present innovative approaches of thin and/or flexible thermal energy harvesters for smart and autonomous sensor network applications. The harvester system will be based on the collaborative work of interrelated energy nodes/units, which will be either piezo-thermofluidic converters (use of rapid thermal cycles of a working fluid) or piezo-thermomechanic converters (use of the mechanical energy developed by rapid snapping of micro-switches). The two kinds of energy nodes convert a heat flux into storable electrical energy through a piezoelectric transducer. Miniaturization of the energy nodes will lead to increased thermal transfer rates and consequently increased harvested power. To effectively use thermal energy sources in varying environments, the nodes will be adaptive versus different thermal gradients (in a predefined temperature range) and will possibly influence each other. The concept is unique in the sense that it is based on a matrix structure of micro or mini energy nodes which will work together in a collective approach to optimize the harvested energy, and which do not require the use of radiators as classical Seebeck approach, thanks to the controlled thermal resistance. This opens the door to new properties and features of the object, with better performances. It could therefore be declined on flexible substrates, allowing conformability around the sources of potential heat for low power applications.
    Silicon Nanoelectronics Workshop (SNW), 2012 IEEE; 01/2012
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    ABSTRACT: Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-V<sub>T</sub> regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations.
    Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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    C. Guerin, V. Huard, A. Bravaix
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    ABSTRACT: This paper presents a theoretical framework about interface state creation rate from Si–H bonds at the Si / Si O <sub>2</sub> interface. It includes three main ways of bond breaking. In the first case, the bond can be broken, thanks to the bond ground state rising with an electrical field. In two other cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows one to physically model the reliability of metal oxide semiconductor field effect transistors, and particularly negative bias temperature instability permanent part, and channel hot carrier to cold carrier damage.
    Journal of Applied Physics 07/2009; · 2.21 Impact Factor
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    ABSTRACT: A general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation.
    Reliability Physics Symposium, 2009 IEEE International; 05/2009
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    ABSTRACT: Channel hot-carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40 nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V<sub>BS</sub>. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V<sub>GS</sub>, V<sub>DS</sub> (V<sub>BS</sub>) conditions as a single I<sub>DS</sub> lifetime dependence is observed with V<sub>GD</sub> > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I<sub>DS</sub>) and multi vibrational excitation (higher I<sub>DS</sub>) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V<sub>BS</sub> = -V<sub>DD</sub> in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V<sub>BS</sub> = -V<sub>DD</sub>/2 for design reliability.
    Reliability Physics Symposium, 2009 IEEE International; 05/2009
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    ABSTRACT: The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.
    Reliability Physics Symposium, 2008. IRPS 2008. IEEE International; 06/2008
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    ABSTRACT: We have developed a two-dimensional noise model based on a Green's function approach. This model allows slow trap density profiles to be determined. The model was applied in the investigation of low- frequency degradation of MOSFETs stressed by hot- carriers, and the generated slow oxide trap density profiles were deduced. For short stress times, the generated traps were localized in the LDD regions, whereas in the case of long stress times, traps were created in both the LDD and the channel regions.
    Ultimate Integration of Silicon, 2008. ULIS 2008. 9th International Conference on; 04/2008
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    ABSTRACT: A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes.
    IEEE Transactions on Device and Materials Reliability 01/2008; · 1.52 Impact Factor
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    ABSTRACT: From extensive set of silicon data presented in this study, we report a new way of understanding and modeling various aspects of NBTI degradation from transistor to product level. This work opens new paths for both relevant process improvements and product optimization.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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    ABSTRACT: A novel composite model had been recently introduced to physically explain the mean pMOS threshold voltage shift (V<sub>TP</sub>) induced by NBTI degradation at transistor level in a quantitative way. This model is here extended to include the statistical variations introduced by intrinsic fluctuations. In a second time, the model is extrapolated up to SRAM arrays by analyzing the SRAM bitcell sensitivity to transistor degradation. This approach allows quantitative prediction of NBTI-induced V<sub>MIN</sub> variations and access time T<sub>aa</sub> degradation during burn-in operations. The key findings include (a) demonstration of non-normality of V<sub>TP</sub> shift distribution (b) NBTI contribution to product V<sub>MIN</sub> drift arises from both mean V<sub>TP</sub> drift but also from increased V<sub>TP</sub> dispersion, and (c) V<sub>TP</sub> shift non-normality is smoothed out at product level by time-zero variation of the six transistors of the SRAM bitcell.
    Reliability Physics Symposium, 2008. IRPS 2008. IEEE International; 01/2008
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    ABSTRACT: In this paper, we propose to distinguish the distinct carrier degradation modes as a function of the energy range developing a complete lifetime extrapolation technique down to the low voltage operation. This provides a starting point of a more accurate modeling of CHC effects during product operations. This work shows that CHC effects in nMOSFET consist in three different regimes depending on the gate voltage (Vg). A simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions was detailed for each regime. We also propose an answer to the contradictory debate of the respective contributions of electron-electron scattering (EES) (Rauch et al., 2001) and the multiple vibrational excitation (MVE) (Hess et al., 1999) to CHC effects in the low energy range.
    Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the; 08/2007
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    C. Guerin, V. Huard, A. Bravaix
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    ABSTRACT: In this paper, we confirm that the energy is the driving force of hot-carrier effects. In high-energy long-channel case, the energy-driven paradigm allows to retrieve lucky electron model-like equations although the explanations are different. When the energy is lowered, high-energy electrons generated by electron-electron scattering become the dominant contribution to the degradation. Finally, for even lower energy, multiple vibrational excitation mechanism starts taking the lead.
    IEEE Transactions on Device and Materials Reliability 07/2007; · 1.52 Impact Factor
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    ABSTRACT: This work reports for the first time a new positive bias temperature instability (PBTI) degradation mode in n-channel MOSFETs related to the introduction of plasma nitridation process step. The degradation is explained only by interface traps creation, differently to NBTI on p-channel MOSFETs where hole trapping might be dominant
    Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
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    ABSTRACT: This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing during a particular condition of degradation. In particular, we gain critical insights into recovery phenomena, which are observed during certain conditions of CHC degradation (Mistry et al., 1991) as well as during NBTI (Rangan, 2003). These findings set the stage for consistent physical models for degradation as well as for design simulation under multiple operating modes
    Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
  • C. Guerin, V. Huard, A. Bravaix
    [show abstract] [hide abstract]
    ABSTRACT: In this work, we confirm that the energy is the driving force of hot carrier effects. In the high energy-, long channel-case, the LEM picture is still valid. But when the energy is lowered, high energy electrons generated by electron-electron scattering (EES) become the dominant contribution to the degradation. Finally, for even lower energy, the hot carrier degradation becomes a composite mode combining both multiple vibrational excitation (MVE) mechanism (Hess, 1999) and medium-energy electrons heated by EES (Rauch, 2001)
    01/2007;
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    C. Guerin, V. Huard, A. Bravaix
    [show abstract] [hide abstract]
    ABSTRACT: In this work, we confirm that the energy is the driving force of Hot Carrier effects. When the energy is high, the Energy-driven framework allows to retrieve Lucky Electron Model-like equations. But when the energy is lowered, high energy electrons generated by Electron-Electron Scattering become the dominant contribution to the degradation. For even lower energy Multiple Vibrational Excitation mechanism starts taking the lead.
    Microelectronic Engineering 01/2007; 84:1938-1942. · 1.22 Impact Factor
  • Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. 01/2007;
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    ABSTRACT: From extensive set of silicon data presented in this study, we report a new way of understanding and modeling various aspects of NBTI degradation from transistor to product level. This work opens new paths for both relevant process improvements and product optimization.
    01/2007: pages 797-800; , ISBN: 978-1-4244-1507-6
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    ABSTRACT: Practical and accurate Design-in Reliability methodology has been developed for designs on 90-45nm technology to quantitatively assess the degradation due to Hot Carrier and Negative Bias Temperature Instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology illustrating the capabilities of the methodology as well highlighting the impacts of the two degradations modes.
    01/2007: pages 191-200; , ISBN: 9783540744412
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    ABSTRACT: This work shows that channel hot carrier (CHC) in nMOSFET consists in two different regimes depending on the gate voltage (V<sub>g</sub>). At low V<sub>g</sub>, a simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions will be detailed. At high V<sub>g</sub>, the second degradation mode becomes worse depending on V<sub>d</sub>. This work focuses on the worst case degradation determination and the model effects on the device lifetime prediction in relation to the CHC degradation mechanisms. A combined and complementary use of charge pumping (CP) and direct current current voltage (DCIV) allows us to obtain the spatial interface traps (Nit) localization giving more information on Nit impact on linear transistor parameters degradation
    Integrated Reliability Workshop Final Report, 2006 IEEE International; 10/2006