C.W. Jeong

Publications (13)1.66 Total impact

• Conference Proceeding: Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)

  D.H. Kang, J.S. Kim, Y.R. Kim, Y.T. Kim, M.K. Lee, Y.J. Jun, J.H. Park, F. Yeung, C.W. Jeong, J. Yu, [......], J.I. Kim, Y.T. Oh, K.W. Lee, S.P. Koh, S.H. Eun, N.B. Kim, G.H. Koh, G.T. Jeong, H.S. Jeong, Kinam Kim
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  ABSTRACT: Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge₂Sb₂Te₅ and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.
  VLSI Technology, 2007 IEEE Symposium on; 07/2007
• Article: Full Integration of Highly Reliable Phase Change Memory With Advanced Ring Type Bottom Electrode Contact

  J. M. Shin, Y. J. Song, D. W. Kang, C. W. Jeong, K. C. Ryoo, J. H. Park, J. H. Oh, J. H. Kong, Jae Park, Y. Fai, [......], J. I. Kim, D. W. Lim, S. S. Park, J. H. Kim, J. S. Kim, Y. T. Kim, G. H. Koh, G. T. Jeong, H. S. Jeong, Kinam Kim
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  ABSTRACT: We successfully developed 256Mb Phase Change Random Access Memory (PRAM) based on 0.10μ m-CMOS technologies using ring type contact. The writing current with uniform CD process variation of Bottom Electrode Contact (BEC) was achieved by improving CMP process and developing core dielectric material. Also, the ring type contact scheme provided strong reliability such as the cycling endurance and data retention time for 256 Mb high density PRAM.
  Integrated Ferroelectrics 03/2007; 90(1):88-94. · 0.30 Impact Factor
• Conference Proceeding: Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology

  J.H. Oh, J.H. Park, Y.S. Lim, H.S. Lim, Y.T. Oh, J.S. Kim, J.M. Shin, Y.J. Song, K.C. Ryoo, D.W. Lim, [......], J.H. Kim, J. Yu, F. Yeung, C.W. Jeong, J.H. Kong, D.H. Kang, G.H. Koh, G.T. Jeong, H.S. Jeong, Kinam Kim
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  ABSTRACT: Fully functional 512Mb PRAM with 0.047mum² (5.8F²) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge₂Sb₂Te₅. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Conference Proceeding: Advanced ring type contact technology for high density phase change memory

  Y.J. Song, J.H. Park, S.Y. Lee, Jae-Hyun Park, Y.N. Hwang, S.H. Lee, K.C. Ryoo, S.J. Ahn, C.W. Jeong, J.M. Shin, W.C. Jeong, K.H. Koh, G.T. Jeong, H.S. Jeong, K.N. Kim
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  ABSTRACT: Advanced bottom electrode contact (BEC) scheme was successfully developed for fabricating reliable high density 64 Mb PRAM by using ring type contact scheme. This advanced ring type BEC scheme was prepared by depositing very thin TiN films inside a contact hole, and then core dielectrics was uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce a reset current with low set resistance, and also maintain a uniform cell distribution. Thus, it is clearly demonstrated that the ring type BEC technology can exhibit strong feasibility of high density 256 Mb PRAM and beyond.
  Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
• Conference Proceeding: Highly reliable 50nm contact cell technology for 256Mb PRAM

  S.J. Ahn, Y.N. Hwang, Y.J. Song, S.H. Lee, S.Y. Lee, J.H. Park, C.W. Jeong, K.C. Ryoo, J.M. Shin, Y. Fai, J.H. Oh, G.H. Koh, G.T. Jeong, S.H. Joo, S.H. Choi, Y.H. Son, J.C. Shin, Y.T. Kim, H.S. Jeong, Kinam Kim
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  ABSTRACT: Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10μm CMOS technology.
  VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
• Conference Proceeding: Process technologies for the integration of high density phase change RAM

  G.T. Jeong, Y.N. Hwang, S.H. Lee, S.Y. Lee, K.C. Ryoo, J.H. Park, Y.J. Song, S.J. Ahn, C.W. Jeong, Y.-T. Kim, H. Horii, Y.H. Ha, G.H. Koh, H.S. Jeong, Kinam Kim
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  ABSTRACT: Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.
  Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on; 06/2005
• Conference Proceeding: Integration technologies for scalable high density MRAM

  J H Park, W.C. Jeong, J H Oh, C.W. Jeong, J.M. Shin, Y.N. Hwang, S J Ahn, S H Lee, S Y Lee, K.C. Ryoo, Jonghyun Park, F. Yang, G.H. Koh, G.T. Jeong, H.S. Jeong, Kinam Kim
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  ABSTRACT: We investigate the key factors for scalable high density MRAM. Specifically we examine problems such as large switching field, small sensing margin and writing disturbance following a decrease in size. We demonstrate these problems and suggest several solutions for realizing high density MRAM.
  VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
• Conference Proceeding: Highly manufacturable high density phase change memory of 64Mb and beyond

  S.J. Ahn, Y.J. Song, C.W. Jeong, J.M. Shin, Y. Fai, Y.N. Hwang, S.H. Lee, K.C. Ryoo, S.Y. Lee, J.H. Park, H. Horii, Y.H. Ha, J.H. Yi, B.J. Kuh, G.H. Koh, G.T. Jeong, H.S. Jeong, Kinam Kim, B.I. Ryu
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  ABSTRACT: Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge₂Sb₂Te₅ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.
  Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
• Conference Proceeding: Integration and cell characteristics for high density PRAM

  K.C. Ryoo, Y.N. Hwang, S H Lee, S Lee, S J Ahn, Y.J. Song, J H Park, C.W. Jeong, J.M. Shin, W.C. Jeong, K.H. Koh, G.T. Jeong, H.S. Jeong, K N Kim
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  ABSTRACT: A 64 Mb phase change random access memory, based on 0.18 μm technology is developed. We proposed several key factors such as BEC and GST cell size, contributing to stabilization of writing current for reversible cell transition. By reducing writing current to 1.1 mA through such optimization, we have developed a 64 Mb PRAM. With memory functions and reliability tests, the feasibility for developing high-density 64 Mb PRAM is presented.
  Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European; 10/2004
• Article: A new reference signal generation method for MRAM using a 90-degree rotated MTJ

  W.C. Jeong, H.J. Kim, J.H. Park, C.W. Jeong, E.Y. Lee, J.H. Oh, G.T. Jeong, G.H. Koh, H.C. Koo, S.H. Lee, S.Y. Lee, J.M. Shin, H.S. Jeong, Kinam Kim
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  ABSTRACT: A new reference signal generation method for high-density MRAM is reported. 0.4×0.8 μm² magnetic tunnel junction (MTJ) elements were successfully integrated with 0.24-μm CMOS technology. By using a 90-degree rotated MTJ as a new reference signal generator, the reference resistance could be always located in the exact midpoint between high-resistance state R_H and low-resistance state R_L regardless of applied voltage. When tested in 8×8 MTJ arrays, it is found to show good fidelity to our expectations. So it is supposed that this new method is more favorable for high-density MRAM.
  IEEE Transactions on Magnetics 08/2004; · 1.36 Impact Factor
• Conference Proceeding: Full integration and cell characteristics for 64Mb nonvolatile PRAM

  S.H. Lee, Y.N. Hwang, S.Y. Lee, K.C. Ryoo, S.J. Ahn, H.C. Koo, C.W. Jeong, Y.-T. Kim, G.H. Koh, G.T. Jeong, H.S. Jeong, Kinam Kim
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  ABSTRACT: We have integrated a 64Mb nonvolatile random access memory using phase transition phenomena. Based on 0.18μm-CMOS technologies, the vertical contact typed memory cell is fabricated. The device density can be sharply increased with decreasing the writing current and the GST size. But for reduction of writing current, issues including set and interface resistances should be stabilized. Additionally, our results also show the feasibility of 256Mb nonvolatile PRAM with writing time below 100ns.
  VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
• Conference Proceeding: PRAM process technology

  G.H. Koh, Y.N. Hwang, S.H. Lee, S.Y. Lee, K.C. Ryoo, J.H. Park, Y.J. Song, S.J. Ahn, C.W. Jeong, F. Yeung, Y.-T. Kim, J.-B. Park, G.T. Jeong, H.S. Jeong, K. Kim
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  ABSTRACT: PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18μm CMOS technology.
  Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
• Conference Proceeding: Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

  Y.J. Song, K.C. Ryoo, Y.N. Hwang, C.W. Jeong, D.W. Lim, S.S. Park, J.I. Kim, J.H. Kim, S.Y. Lee, J.H. Kong, [......], J.S. Kim, J.M. Shin, Y. Fai, G.H. Koh, G.T. Jeong, R.H. Kim, H.S. Lim, I.S. Park, H.S. Jeong, Kinam Kim
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  ABSTRACT: Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge₂Sb₂Te₅ (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond
  VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;