C H Tsai

Publications (19)0 Total impact

• Conference Proceeding: Ti/HfO2 based RRAM operation voltage scaling for embedded memory

  C. H. Tsai, F. T. Chen, H. Y. Lee, Y. S. Chen, K. H. Tsai, T. Y. Wu, S. Z. Rahaman, P. Y. Gu, W. S. Chen, P. S. Chen, Z. H. Lin, P. L. Tseng, W. P. Lin, C.H. Lin, S. S. Sheu, M. -J. Tsai, T. K. Ku
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  ABSTRACT: Consumer gadgets make up the fastest growing market for electronic devices today. These products will rely more and more on embedded storage-type memory, which can store system and processing data without impacting standby power consumption. For embedded memory applications, including microcontrollers, automotive, and mobile code storage applications, NOR flash is a popular choice for its non-volatility and fast read time on the order of nanoseconds. However, its operation voltage is larger than 10V, and the write speed exceeds 10 microseconds. Although increasing density is not a key requirement for process scaling of embedded memory down to advanced nodes, the operation voltage needs to be reduced to continually lower power consumption and to match foundry offerings in the logic and mixed-signal sectors, both in the core voltages and the I/O voltages. Resistive random-access memory (RRAM) is proposed to be such a scalable embedded memory technology. RRAM offers the advantages of CMOS process compatibility, high speed, high endurance, low-voltage operation, and high cell density. In this article, we demonstrate that the operation voltage can be reduced to under 1V in the Ti/HfOx RRAM system with a multi-level RESET operation strategy, while keeping the write speed to less than 2 microseconds, opening up opportunities for RRAM in embedded memory applications.
  China Semiconductor Technology International Conference (CSTIC) 2013; 03/2013
• Conference Proceeding: Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance

  H.Y. Lee, Y.S. Chen, P.S. Chen, P.Y. Gu, Y.Y. Hsu, S.M. Wang, W.H. Liu, C.H. Tsai, S.S. Sheu, P.C. Chiang, W.P. Lin, C.H. Lin, W.S. Chen, F.T. Chen, C.H. Lien, M. Tsai
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  ABSTRACT: The memory performances of the HfO_X based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 10¹⁰ cycles.
  Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
• Conference Proceeding: Design of high-performance and highly reliable nMOSFETs with embedded Si:C S/D extension stressor(Si:C S/D-E)

  S.S. Chung, E.R. Hsieh, P.W. Liu, W.T. Chiang, S.H. Tsai, T.L. Tsai, R.M. Huang, C.H. Tsai, W.Y. Teng, C.I. Li, T.F. Kuo, Y.R. Wang, C.L. Yang, C.T. Tsai, G.H. Ma, S.C. Chien, S.W. Sun
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  ABSTRACT: A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I_D,sat current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%=1.1%), using the poly-gate 40 nm-node Si:C/eSiGe S/D CMOS technology. Moreover, PBTI effect was first observed in this device as a result of carbon impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
  VLSI Technology, 2009 Symposium on; 07/2009
• Conference Proceeding: A new observation of strain-induced slow traps in advanced CMOS technology with process-induced strain using random telegraph noise measurement

  M.H. Lin, E.R. Hsieh, S.S. Chung, C.H. Tsai, P.W. Liu, Y.H. Lin, C.T. Tsai, G.H. Ma
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  ABSTRACT: In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I_D-RTN (drain current random telegraph noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
  VLSI Technology, 2009 Symposium on; 07/2009
• Conference Proceeding: More strain and less stress- the guideline for developing high-end strained CMOS technologies with acceptable reliability

  S.S. Chung, E.R. Hsieh, D.C. Huang, C.S. Lai, C.H. Tsai, P.W. Liu, Y.H. Lin, C.T. Tsai, G.H. Ma, S.C. Chien, S.W. Sun
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  ABSTRACT: In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65 nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (N_it) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
  Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
• Conference Proceeding: Schottky Source/Drain CMOS Device Optimization with Dopant-Segregated NiPt Silicide

  Y.T. Huang, P.W. Liu, W.T. Chiang, T.L. Tsai, C.H. Tsai, C.T. Tsai, G.H. Ma
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  ABSTRACT: We have successfully demonstrated an optimized dopant- segregated Schottky (DSS) source/drain CMOS technology featuring 35 nm physical gate length and 1.2 nm gate oxide. Several important device characteristics, including sidewall gate junction leakage suppression, short channel effect (SCE) control, along with drive current performance, are all investigated in this work. Furthermore, we notice that halo implant process is indispensable for providing the wider process window, which is realized by compensating the sensitive dopant segregation implantation (DSI) process. Without any supplement of additional process-induced stress, the DSS N/PMOS drive current of 100 nA/um and 510 uA/um at I_off=100 nA/um and V_dd=1.2 V are obtained. Moreover, an 11% I_on improvement can be achieved in the optimized DSS NMOS.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
• Conference Proceeding: Optimal PD-SOI Technology for High Performance Applications

  W.T. Chiang, P.W. Liu, Y.T. Huang, T.L. Tsai, Y.H. Lin, C.H. Tsai, Y. Laplanche, J.-L. Pelloie, C.T. Tsai, G.H. Ma
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  ABSTRACT: We present an optimal partially-depleted silicon-on-insulator (PD-SOI) platform, which demonstrates superior performance of SOI over bulk technology. Device optimization is performed in terms of circuit switch speed and power consumption through channel and S/D engineering. Fundamental device characteristics, SRAM yields, reliability assessment, and physical IP qualification for our PD-SOI platform are all validated to demonstrate the feasibility for high performance applications. Performance comparison based on circuit simulation clearly shows the SOI advantage on area and power consumption. In addition, the strained-SOI (sSOI) technology is developed for further SOI performance enhancement.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
• Conference Proceeding: Improved Layout Dependence in High Performance SiGe Channel CMOSFETs

  P.W. Liu, W.T. Chiang, Y.T. Huang, T.L. Tsai, C.H. Tsai, C.T. Tsai, G.H. Ma
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  ABSTRACT: The device degradation problem due to compressive STI in devices with narrow width or small diffusion length can be greatly relieved in SiGe channel devices with the post-STI epitaxy process. The (110)SiGe PMOS realizes 77% current gain over (100)Si PMOS at 1um gate width, and current gain is increased to 112% at 0.12um gate width. A 42% current improvement in (100)SiGe NMOS at 0.12um gate width is also reported. Moreover, for diffusion length ranging from 2.71um to 0.26um, less than 4% current variation is obtained in SiGe channel devices compared to the 8~12% current variation in Si channel devices. The improved layout dependence is resulted from the lower STI stress in post-STI SiGe epitaxy process.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
• Conference Proceeding: The Ballistic Transport and Reliability of the SOI and Strained-SOI nMOSFETs with 65nm Node and Beyond Technology

  E.R. Hsieh, D.W. Chang, S.S. Chung, Y.H. Lin, C H Tsai, C.T. Tsai, G.H. Ma
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  ABSTRACT: In this paper, the device performance in terms of its transport characteristics and reliability of the MOS devices on the SOI and strained-SOI have been examined. For the first time, both the transport and reliability characteristics have been established from experimental SOI and SSOI nMOSFETs. It was characterized by two parameters, the ballistic efficiency and the injection velocity. Experimental verifications on nMOSFETs with both technologies with tensile-stress enhancement have been made. For SSOI devices, it shows the expected drain current enhancements. For the reliability evaluations, SOI shows a smaller lattice such that it exhibits a much worse hot carrier (HC) reliability, while SSOI device shows a poorer interface quality verified from the FN-stress experiment. In general, although SSOI exhibits a worse interface quality while its reliability is much better than that of SOI's. Moreover, SSOI device shows a very high injection velocity as a result of the high strain of the device which makes it successful for drain current enhancement.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
• Conference Proceeding: Technology Roadmaps on the Ballistic Transport in Straln Engineered Nanoscale CMO0S Devices

  S.S. Chung, Y.J. Tsai, C.H. Tsai, P.W. Liu, Y.H. Lin, C.T. Tsai, G.H. Ma, S.C. Chien, S.W. Sun
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  ABSTRACT: As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the I_ON current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65 nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100 nm regime.
  Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
• Conference Proceeding: Circuit Performance Optimization in Advanced PD-SOI CMOS Development

  W.T. Chiang, Y T Huang, P.W. Liu, C H Wu, C.M. Su, Y S Huang, C H Tsai, Y. Laplanche, J.-L. Pelloie, C.T. Tsai, G.H. Ma
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  ABSTRACT: Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power consumption. The effects of several key factors, such as threshold voltage (Vth), pre-amorphization implantation (PAI), and silicon film thickness (Tsi), are fully investigated and optimized to achieve optimal ring-oscillator performance. We found that well-designed PAI improves circuit delay vs. leakage characteristics, while decreasing Tsi also reduces the propagation delay. We then present the optimized AC performance for a variety of circuits, as well as the DC performance, the SRAM characteristics, and the reliability assessment.
  SOI Conference, 2007 IEEE International; 11/2007
• Conference Proceeding: 65nm CMOS BULK to SOI comparison

  J.L. Pelloie, Y. Laplanche, T.F. Chen, Y.T. Huang, P.W. Liu, W.T. Chiang, M.Y.T. Huang, C.H. Tsai, Y.C. Cheng, C.T. Tsai, G.H. Ma
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  ABSTRACT: SOI is today mainly used for high-speed CPU applications. The advantages brought by SOI are still questioned or not clearly understood and little information has been published about the comparison between bulk and SOI CMOS. First reason is that this comparison to be representative must be done for same process features such as gate length and gate oxide thickness, second reason is that designing the same circuit in both bulk and SOI requires a significant investment. 65nm CMOS bulk and SOI both developed at UMC 12" facility with same process features are compared in this paper.
  SOI Conference, 2007 IEEE International; 11/2007
• Conference Proceeding: SiGe Channel CMOSFETs Fabricated on (110) Surfaces with TaC/HfO2 Gate Stacks

  P.W. Liu, Y.H. Lin, W.T. Chiang, C H Tsai, L.-W. Cheng, C.T. Tsai, G.H. Ma
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  ABSTRACT: The promising potential of SiGe channel for next generation CMOSFETs applications has been demonstrated on (110) surfaces. SiGe channel CMOSFETs with TaC/FffO₂ gate stack were fabricated on (110) surfaces for the first time. By introducing SiGe for channel material, the mobility of n/p-MOSFETs with TaC/HfO₂ gate stacks can be greatly improved compared to Si channel devices with the same metal-gate/high-K gate stacks. The (110) SiGe channel n/p-MOSFETs with TaC/FffO₂ gate stacks show 1.8x and 2.4x mobility enhancements over (110) Si devices with TaC/HfO₂. The 23% propagation time delay improvement of ring oscillators fabricated with (110) SiGe channel CMOSFETs and poly/oxynitride gate stacks also proves the feasibility of (110) SiGe channel.
  VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
• Conference Proceeding: Strain Effects of Si and SiGe Channel on (100) and (110) Si Surfaces for Advanced CMOS Applications

  W.T. Chiang, J.W. Pan, P.W. Liu, C H Tsai, C.T. Tsai, G.H. Ma
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  ABSTRACT: High performance SiGe channel CMOS on (100) and (110) Si surfaces with process-induced strained-Si technologies was fabricated and compared to Si channel devices. The mechanism of stress-induced performance enhancements in SiGe channel devices on both (100) and (110) surfaces was systematically investigated. Device-level piezoresistance coefficients for Si and SiGe channels were extracted from CMOS transistors with external mechanical stress applied. The results were consistent with device drive current enhancement induced by the CESL strained scheme.
  VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
• Conference Proceeding: The Channel Backscattering Characteristics of Sub-100nm CMOS Devices with Different Channel/Substrate Orientations

  Y.J. Tsai, S.S. Chung, P.W. Liu, C.H. Tsai, Y.H. Lin, C.T. Tsai, G.H. Ma, S.C. Chien, S.W. Sun
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  ABSTRACT: The channel backscattering and injection velocity of carriers in advanced CMOS devices are the two key parameters for achieving high drain current enhancement. For the first time, an extensive study of these transport parameters for different substrate orientations has been evaluated for both nMOSFET and pMOSFET. By suitably choosing the substrate orientation, it may achieve a reduced backscattering and an increased injection velocity, which is preferable for designing high performance logic CMOS devices. Results show that, in pMOSFET, (110) substrate is preferred and current enhancement can be greatly enhanced in the <112> channel. In comparison, (110) substrate in nMOSFET has an adverse effect in reducing driving current as a result of poorer transport characteristics. Therefore, (100) substrate is expected for nMOSFET design. A guideline is then summarized for the optimum design of high performance CMOS devices.
  VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
• Conference Proceeding: Mobility and Strain Effects on /(110) SiGe channel pMOSFETs for High Current Enhancement

  J.W. Pan, P.W. Liu, T.Y. Chang, W.T. Chiang, C.H. Tsai, Y.H. Lin, C.T. Tsai, G.H. Ma, S.C. Chien, S.W. Sun
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  ABSTRACT: Mobility and strain mechanisms of SiGe channel pMOSFETs fabricated with <110> channel direction on (110) Si substrate (<110>/(110) SiGe channel) have been studied in details for the first time. The combination of substrate orientation, high mobility channel material and extrinsic stained-Si process demonstrates the ultra high mobility enhancement and results in 80% current gain. The piezoresistance coefficients of <110>/(110) SiGe channel p-MOSFETs were also studied to analyze the strain effect on current enhancement. We also compared the derived piezoresistance coefficients results of SiGe channel on (100) and (110) surfaces
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Conference Proceeding: New Observations on the Uniaxial and Biaxial Strain-Induced Hot Carrier and NBTI Reliabilities for 65nm Node CMOS Devices and Beyond

  Steve S. Chung, D. C. Huang, Y. J. Tsai, C. S. Lai, C. H. Tsai, P. W. Liu, Y. H. Lin, C. T. Tsai, G. H. Ma, S. C. Chien, S. W. Sun
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  ABSTRACT: In this paper, new observations on the uniaxial and biaxial strain-induced hot carrier reliability and/or NBTI in nMOSFET and pMOSFET respectively have been reported for the first time. Uniaxial and biaxial strained nMOSFET and pMOSFET have been extensively examined. Different mechanisms are responsible for different strains in nMOSFET and pMOSFET. For the nMOFETs, it was found that uniaxial strain device has comparable HC reliability with the control device, while biaxial SiGe-strained device exhibits a much worse reliability. This is related to a large impact ionization rate in a biaxial strain which leads to a much worse reliability. For the pMOSFETs, either uniaxial or biaxial strained device shows a comparable amount of HC degradation, while SiGe S/D strained structure might be better considering process complexity, performance, and reliability. Although NBTI is still a great concern in SiGe S/D devices, embedded SiGe S/D technique can improve greatly the device NBTI reliability. These results provide a valuable guideline for the present 65nm and beyond CMOS device design with focus on the strain engineering.
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Conference Proceeding: Single stress liner for both NMOS and PMOS current enhancement by a novel ultimate spacer process

  Y.C. Liu, J.W. Pan, T.Y. Chang, P.W. Liu, B.C. Lan, C.H. Tung, C.H. Tsai, T.F. Chen, C.J. Lee, W.M. Wang, [......], L.W. Cheng, T.M. Shen, S.C. Chiang, M.F. Lu, W.T. Chang, Y.H. Luo, D. Nayak, D. Gitlin, H.L. Meng, C.T. Tsai
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  ABSTRACT: For the first time, 75% and 7% drive current improvement is simultaneously achieved in both N/PMOS by adopting ultimate spacer process (USP) with a single stress liner. High out-of-plane stress in the channel accounts for the simultaneously enhanced drive current in N/PMOS. A 15% speed enhancement without compromising yield and product qualification in field-programmable gate arrays (FPGA) confirms immediate manufacturing feasibility of USP. This process provides a unique approach to significantly enhance device performance for 65nm CMOS technology and beyond. Extreme current increase of 25% in NMOS and 35% in PMOS can be achieved by applying additional strain enhancement methods
  Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
• Conference Proceeding: Unique Ultra Shallow Junction Scheme with Conventional Activation Process

  C.H. Tsai, B.C. Lan, Y.H. Lin, W.T. Chiang, T.Y. Chang, P.W. Liu, J.W. Pan, Y.C. Liu, J.L. Tsai, T.F. Chen, C.T. Tsai
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  ABSTRACT: A unique ultra shallow junction scheme featured with integrating diffusion barrier into eSiGe:B strained pMOSFETs has been demonstrated. Embedded diffusion barrier (EDB) drastically suppresses boron out-diffusion from subsequent thermal treatment, thus resulting in superior short channel control. This approach enables the formation of ultra shallow junction, over 30% junction depth reduction, while simultaneously maintaining low extension resistance using conventional activation process only. Furthermore, eSiGe:B with embedded diffusion barrier (eSiGe:B w/ EDB) scheme can still retain local stress and enhanced pMOSFETs current. Device performance and barrier layer characteristics of eSiGe:B w/ EDB scheme are also reported in this work
  VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;