G.H. Ma

National Chiao Tung University, Hsinchu, Taiwan, Taiwan

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Publications (30)2.54 Total impact

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    ABSTRACT: A ¿hybrid¿ high-k/metal gate (HK/MG) integration scheme is proposed in this paper to accomplish HP (high performance) 28 nm CMOSFETs by integrating gate-first/gate-last (GF/GL) techniques for N/PFET, respectively. For NFET, remarkable mobility (95% of n<sup>+</sup>poly/SiON@1MV/cm) and low V<sub>TH</sub> (0.25 V) was achieved through optimized HfO<sub>2</sub> high-k, TiN metal and LaO<sub>x</sub> capping layer processes. For PFET, an extra 30% performance improvement and a low V<sub>TH</sub> (0.25 V) were achieved by GL process as a result of strain boost and VFB roll-off alleviation.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: The PBTI is an important issue in the high-k dielectric nMOSFET devices in the present CMOS technology. In this paper, Random telegraph noise (RTN) technique was employed to investigate the stressed-induced traps and their correlation to the hot carrier and PBTI effects. It was found that the positions of stress-induced traps (SITs) are mostly located in the high-k layer, but not close to the high-k/SiO2 interface. The SITs under PBTI stress exhibit a larger amount of ΔNS/NS in the ΔID/ID fluctuation as a result of the traps which are generated close to the source side and lead to the VT instability. This new finding is helpful toward the understanding of the BTI effect in high-k gate dielectric MOSFETs.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2010;
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    ABSTRACT: In this paper, the origin of the strained-induced degradation in the MOSFETs with process-induced strain has been investigated by the ID-RTN (Drain Current Random Telegraph Noise) technique. The process-induced strain on devices will make worse the device reliability, as reported. First, the ID-RTN has been employed to study the reliability of two different types of strain devices, i.e., the CESL strain and SiC S/D strain on nMOSFETs. Both CESL and SiC S/D nMOSFETs exhibit poorer reliability compared to bulk devices. However, their impacts to the much worse degradation are different. Results demonstrated that, for the strain in CESL device, it introduced extra mobility scattering in the vertical direction, while in SiC S/D device, the tensile strain along the channel causes an increase of trap generation via the horizontal field only. The CESL process introduces an additional compressive strain vertical to the channel such that it shows much worse reliability than the SiC S/D ones.
    Reliability Physics Symposium (IRPS), 2010 IEEE International; 01/2010
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    ABSTRACT: In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I<sub>D</sub>-RTN (drain current random telegraph noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
    VLSI Technology, 2009 Symposium on; 07/2009
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    ABSTRACT: A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I<sub>D,sat</sub> current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%=1.1%), using the poly-gate 40 nm-node Si:C/eSiGe S/D CMOS technology. Moreover, PBTI effect was first observed in this device as a result of carbon impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
    VLSI Technology, 2009 Symposium on; 07/2009
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    ABSTRACT: In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65 nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (N<sub>it</sub>) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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    ABSTRACT: A new method, called gate current random telegraph noise (I<sub>G</sub> RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, I<sub>G</sub> RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the soft-breakdown (SBD) behavior of a device can be clearly identified. Its I<sub>G</sub> RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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    ABSTRACT: A new yet simple approach, VD,sat method, without complicate temperature measurement setup, has been developed to investigate the carrier transport characteristics for MOSFET devices in the quasi-ballistic regime. It has shown quite good matches with that of Temperature Dependent Method (TDM) developed from the quantum theory. For the first time, the carrier transport properties after HC stress were also examined based on the proposed method. Moreover, VD,sat method has been applied to examine the carrier transport and reliabilities in advanced strain-CMOS devices. In terms of the device performance, the enhancement of the drain current is strongly related to the transport parameter, the injection velocity, Vinj, which serves as a good monitor for the strain design and current enhancement. While, considering the device reliability after the HC stress, ballistic efficiency, Bsat is responsible for the ID degradation as a result of the increase in interface scatterings. Finally, a roadmap of the Vinj from those reported results has been provided which serves as a good reference for designing high performance strain- based CMOS devices.
    01/2009;
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    ABSTRACT: The dopant and thermal interaction on solid phase epitaxy (SPE) formed SiC has been investigated. We have studied the impact on substitutional carbon concentration ([C]sub) from various thermal steps including low temperature anneal, SiGe epitaxy thermal budget, RTP, and laser anneal (LSA). Regarding the integration scheme for implementing embedded SiC (eSiC) S/D on NMOS performance enhancement, both post-LDD and post-S/D schemes were studied. The higher [C]sub in post-LDD scheme was observed and the S/D dopants were found to enhance the carbon precipitation into interstitial with conventional RTP/LSA activation thermal processes. The phosphorous implant is also found to degrade [C]sub in comparison to As implant. The higher [C]sub and proximity to channel of formed eSiC in post-LDD scheme are beneficial to device performance. The fabricated eSiC S/D NMOS shows 31% mobility improvement and 7% current enhancement.
    VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on; 01/2009
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    ABSTRACT: In this paper, we have systematically investigated the factors for performance enhancement on sub-32nm CMOS technology. We report that PMOS gains the drive current by slim spacer, S/D silicide resistance reduction by e-SiGe, and compressive CESL. The three factors improve the PMOS performance by 7%, 10% and 25% respectively. Combined with the three factors can gain the device drive current 30%. In addition, the optimized integration scheme can reduce NMOS extension resistance. The main cause is that post e-SiGe clean processes would loss the extension dopant and increases the extension resistance. We successfully reduce the NMOS total resistance 22% compared to control without compromise PMOS device performance.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2009;
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    ABSTRACT: Metal-oxide-semiconductor capacitors (MOSCs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating hafnium silicate (Hf-silicate) dielectrics were fabricated by using atomic layer deposition (ALD). The electrical properties of these Hf-silicate thin films with various postnitridation annealing (PNA) temperatures were then examined to find the best nitridation condition. It is found that the best conditions to achieve the lowest gate leakage current and best equivalent oxide thickness (EOT) are when PNA is performed at 800 °C in NH3 ambient for 60 s. To understand the obtained film, carrier transportation mechanisms, the temperature dependence of the leakage current was measured from 300 K to 500 K for both gate injection and substrate injection. The result reveals that the leakage mechanisms involve Schottky emission at high temperature and low electrical field and Poole–Frenkle emission at low temperature and high electrical field. The barrier heights of poly-Si/Hf-silicate and Hf-silicate/Si interfaces extracted from Schottky emission are 1.1 eV and 1.04 eV, respectively. The interface traps per unit area, the mean density of interface traps per area and energy and the mean capture cross-section are determined about 8.1 × 1010 cm−2, 2.7 × 1011 cm−2 eV−1 and 6.4 × 10−15 cm−2 using charge pumping method.
    Applied Surface Science 07/2008; 254(19):6127–6130. · 2.54 Impact Factor
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    ABSTRACT: In this paper, the device performance in terms of its transport characteristics and reliability of the MOS devices on the SOI and strained-SOI have been examined. For the first time, both the transport and reliability characteristics have been established from experimental SOI and SSOI nMOSFETs. It was characterized by two parameters, the ballistic efficiency and the injection velocity. Experimental verifications on nMOSFETs with both technologies with tensile-stress enhancement have been made. For SSOI devices, it shows the expected drain current enhancements. For the reliability evaluations, SOI shows a smaller lattice such that it exhibits a much worse hot carrier (HC) reliability, while SSOI device shows a poorer interface quality verified from the FN-stress experiment. In general, although SSOI exhibits a worse interface quality while its reliability is much better than that of SOI's. Moreover, SSOI device shows a very high injection velocity as a result of the high strain of the device which makes it successful for drain current enhancement.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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    ABSTRACT: We present an optimal partially-depleted silicon-on-insulator (PD-SOI) platform, which demonstrates superior performance of SOI over bulk technology. Device optimization is performed in terms of circuit switch speed and power consumption through channel and S/D engineering. Fundamental device characteristics, SRAM yields, reliability assessment, and physical IP qualification for our PD-SOI platform are all validated to demonstrate the feasibility for high performance applications. Performance comparison based on circuit simulation clearly shows the SOI advantage on area and power consumption. In addition, the strained-SOI (sSOI) technology is developed for further SOI performance enhancement.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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    ABSTRACT: The device degradation problem due to compressive STI in devices with narrow width or small diffusion length can be greatly relieved in SiGe channel devices with the post-STI epitaxy process. The (110)SiGe PMOS realizes 77% current gain over (100)Si PMOS at 1um gate width, and current gain is increased to 112% at 0.12um gate width. A 42% current improvement in (100)SiGe NMOS at 0.12um gate width is also reported. Moreover, for diffusion length ranging from 2.71um to 0.26um, less than 4% current variation is obtained in SiGe channel devices compared to the 8~12% current variation in Si channel devices. The improved layout dependence is resulted from the lower STI stress in post-STI SiGe epitaxy process.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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    ABSTRACT: In this paper, we have systematically investigated the impact of the thermal-induced stress relaxation on biaxially strained silicon-on-insulator (SSOI) CMOS. We found that STI anneal would degrade nMOS drive current by 12% but improve pMOS by 17% in long channel SSOI devices. However, skipping LDD anneal would increase extension resistance and cause performance degradation. In addition, it is found that narrow-width devices suffer more serious thermal strain relaxation. After optimizing the thermal process, we successfully demonstrate enhanced sSOI nMOS with 65% transconductance gain at L = 1 um and 15% drive current improvement at L = 40 nm over SOI nMOS.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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    ABSTRACT: We have successfully demonstrated an optimized dopant- segregated Schottky (DSS) source/drain CMOS technology featuring 35 nm physical gate length and 1.2 nm gate oxide. Several important device characteristics, including sidewall gate junction leakage suppression, short channel effect (SCE) control, along with drive current performance, are all investigated in this work. Furthermore, we notice that halo implant process is indispensable for providing the wider process window, which is realized by compensating the sensitive dopant segregation implantation (DSI) process. Without any supplement of additional process-induced stress, the DSS N/PMOS drive current of 100 nA/um and 510 uA/um at I<sub>off</sub>=100 nA/um and V<sub>dd</sub>=1.2 V are obtained. Moreover, an 11% I<sub>on</sub> improvement can be achieved in the optimized DSS NMOS.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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    ABSTRACT: As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the I<sub>ON</sub> current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65 nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100 nm regime.
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
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    ABSTRACT: In this work, for the first time, an abnormal leakage current has been observed in MOSFET with 50 nm channel length and beyond. This effect shows that, in an ultra-short channel MOSFET, sub-threshold swing (SS) and Ioff are decreased for back-biased nMOSFET and pMOSFET. This effect is attributed to the BJT-induced current from the source to the drain. An experimental approach has been used to verify the existence of this BJT current component. As a consequence, this BJT current can be reduced with appropriate control of the SID-to-substrate junction. As an application of the approach to advanced embedded-SiC MOSFET with various splits, it was found that a higher band-offset of SID-to-substrate junction will give rise to a larger the BJT ballistic transport current. This provides us important information on reducing the leakage current for advanced CMOS with 50nm and beyond.
    01/2008;
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    ABSTRACT: SOI is today mainly used for high-speed CPU applications. The advantages brought by SOI are still questioned or not clearly understood and little information has been published about the comparison between bulk and SOI CMOS. First reason is that this comparison to be representative must be done for same process features such as gate length and gate oxide thickness, second reason is that designing the same circuit in both bulk and SOI requires a significant investment. 65nm CMOS bulk and SOI both developed at UMC 12" facility with same process features are compared in this paper.
    SOI Conference, 2007 IEEE International; 11/2007
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    ABSTRACT: An advanced partially-depleted (PD) silicon-on-insulator (SOI) CMOS device was optimized with full consideration of the floating body effect (FBE) using channel and S/D engineering. By adjusting channel and S/D implants' species and dosage, the S/D doping profiles across transistor sidewall junction will be shown to reduce floating body effects and sidewall junction capacitance. Reduced sidewall junction capacitance results in higher performance in AC operation. In this paper we successfully demonstrated the optimized devices that exhibit suppression floating body effect, and lower ring oscillator (RO) static leakage and active power consumption at the same propagation delay.
    SOI Conference, 2007 IEEE International; 11/2007