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Hye Jin Cho,
Byung Young Choi,
Hee Soo Kang,
Suk-Kang Sung,
Tae Hun Kim, Byung-Kyu Cho,
Donguk Choi,
A. Fayrushin,
Jong Ho Lim,
Ji-Hwon Lee,
A.T. Kim,
Hong-Shik Kim,
In Sun Jung,
Yonghan Roh,
Choong-Ho Lee,
Kyucharn Park,
Donggun Park
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ABSTRACT: In this paper, we report the enhanced performance of multi-giga bit NAND flash memory through the combined effects of uniaxial compressive stress and <100>-oriented channel engineering. Using this method, cell current increased more than 29% owing to the mobility enhancement of the narrow width (60 nm) flash cell. Reduced interface trap with the active edge of <100> channel resulted in the endurance characteristic improvement ~5%.
Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE; 11/2006
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ABSTRACT: Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V<sub>th</sub>) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.
IEEE Transactions on Nanotechnology 06/2006; · 2.29 Impact Factor
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Byung Yong Choi,
Choong-Ho Lee,
Yong Kyu Lee,
Hyungcheol Shin,
Jong Duk Lee,
Byung-Gook Park,
Dong-Won Kim,
Suk-Kang Sung,
Se Hoon Lee, Byung-Kyu Cho,
Tae-Yong Kim,
Eun Suk Cho,
Jong Jin Lee,
Donggun Park
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ABSTRACT: The lateral charge distribution on 2-bit SONOS memory can be readily characterized using physically separated twin SONOS structure. The damascene gate and outer sidewall process successfully contribute to make the twin SONOS structure down to 80nm gate regime. Its lateral charge distribution is estimated through the SS and V<sub>th</sub> shifts for forward and reverse reading and confirmed by the comparison with a conventional (non-separated) SONOS structure.
Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on; 04/2006
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Eun Suk Cho,
Choong-Ho Lee,
Tae Yong Kim,
Suk-Kang Sung, Byung-Kyu Cho,
Chul Lee,
Hye Jin Cho,
Yonghan Roh,
Donggun Park,
Kinam Kim,
Byung-Il Ryu
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ABSTRACT: We report for the first time on 256Mb NOR-type body tied FinFET flash memory using Hf silicate IPD (inter poly dielectric) and compare with FinFET flash memory using traditional ONO IPD. An enlarged coupling ratio through Hf silicate IPD enhanced a CHEI (channel hot electron injection) programming speed and made the operation voltage down. And we could obtain a higher erasing speed resulted from HHI (hot hole injection) erase than that of F-N tunneling without degrading endurance characteristics.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: We have achieved an optimal scheme for the practical application of body-tied FinFET for sub 50 nm NOR flash memory. Using this scheme, high program speed (Vt>8V@1mus) and low drain disturbance (DeltaVt=-0.1V@5ms) with a good reliability have been demonstrated. The effects of USC (ultra-shallow conformal) doping and SGHE (secondary generated hot electron) injection on program and drain disturbance characteristics of FinFET cells have been intensively studied. In addition, the (100) channel engineered body-tied FinFET shows manufacturable endurance characteristics
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
