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ABSTRACT: A novel two-stage algorithm for constructing the orthogonal concavity tree (OCT) of a digital object is proposed. In Stage I, it derives the minimum-area orthogonal cover of the object. In Stage II, it constructs the orthogonal hull from the ortho-cover, and while doing so, extracts the orthogonal concavities in an iterative manner. Nested concavities, if any, are obtained by considering each concavity and its ortho-hull, and the resultant concavities can be used to prepare the OCT. A smaller grid size captures the finer concavities of the underlying object, whereas a larger grid size results in fewer and coarser concavities. Experimental results demonstrate the efficacy and elegance of the proposed algorithm.
Emerging Applications of Information Technology (EAIT), 2011 Second International Conference on; 03/2011
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ABSTRACT: Packet filtering is the one of the major contemporary firewall design techniques. An important design goal is to arrive at the decision at the packet only. Implementation of such packet filter using Binary Decision Diagram (BDD) gives more advantages in terms of memory usage and look up time. In the case of the list-based packet filter firewall where rules are checked one by one for each incoming packet, the time taken to decide on a packet is proportional to the number of rules. The performance is improved with rule promotion but that itself a slow procedure. In this work we present a BDD-based approach which gives much better result in terms of number of comparisons or accesses the rule list make. Results on 1 million packets show that for most-accept packets, on an average, 75% reduction happens in such comparisons when BDD-based approach is used over list-based with promotion approach. For most-reject packets this reduction is nearly 34%.
Students' Technology Symposium (TechSym), 2011 IEEE; 02/2011
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ABSTRACT: A biodroplet transportationchemical analysis is based on several laboratory protocols that require repeated mixing of samples with reagents. Sample preparation and analyte identification steps in such bioassays often involve mixing for solution preparation, i.e., various fluids are to be mixed in a certain volumetric ratio in their resulting mixture. We present an efficient approach for automated mixing of three or more fluids on a droplet based digital micro fluidic biochip and design a layout for implementing this algorithm. The proposed method reduces the droplet transportation time from boundary reservoirs to on chip mixers as well as cross-contamination among overlapping droplet routing paths. Simulation of several example solutions reveals encouraging results.
VLSI Design (VLSI Design), 2011 24th International Conference on; 02/2011
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ABSTRACT: Digital microfluidic(DMF) biochips have emerged recently as a viable platform of implementing conventional laboratory-based biochemical procedures. These tiny chips are able to manipulate nanoliter volume of discrete fluid dropletson an electrode array via electrical actuation. However, with the increasing dimension of the array, the number of external control pins connected to the electrodes may increase significantly. Several pin-constrained biochip design techniques have been proposed earlier for controlling the electrodes through a small number of pins, a short review of which is presented in this paper. An important design problem in such a chip is interconnection wire routing for the identically controlled electrodes. To address this problem, we propose a new scheme of layered wire routing for a special class of pin-constrained biochips that can concurrently execute multiple instances of the same bioassay to increase throughput. We also describe a hierarchical routing scheme to ensure scalability.
Electronic System Design (ISED), 2010 International Symposium on; 01/2011
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ABSTRACT: Digital micro fluidic technology is now being extensively used for implementing a lab-on-a-chip. Micro fluidic biochips are often used for safety-critical applications, clinical diagnosis, and for genome analysis. Thus, devising effective and faster testing methodologies to warrant correct operations of these devices after manufacture and during bioassay operations, is very much needed. In this paper, we propose a technique to obtain the route plan of a test droplet for the purpose of structural testing of biochips. The technique is applicable to fully reconfigurable arrays and application specific biochips. We propose an improved eulerization technique to implement the test plan based on a graph model of the chip. The optimal eulerization can be abstracted in terms of the classical Chinese postman problem. The Euler tour can then be identified using a cycle decomposition method, which is easy to implement. This can also be used in phase-based test planning leading to significant savings in testing time. The method provides a unified approach towards unidirectional structural testing and can be easily adapted to design an improved droplet routing procedure for bidirectional functional testing of digital micro fluidic biochips.
Test Symposium (ATS), 2010 19th IEEE Asian; 01/2011
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ABSTRACT: The recent emergence of lab-on-a-chip (LoC) technology has led to a paradigm shift in many healthcare-related application areas, e.g., point-of-care clinical diagnostics, high-throughput sequencing, and proteomics. A promising category of LoCs is digital microfluidic (DMF)-based biochips, in which nanoliter-volume fluid droplets are manipulated on a 2-D electrode array. A key challenge in designing such chips and mapping lab-bench protocols to a LoC is to carry out the dilution process of biochemical samples efficiently. As an optimization and automation technique, we present a dilution/mixing algorithm that significantly reduces the production of waste droplets. This algorithm takes O ( n ) time to compute at most n sequential mix/split operations required to achieve any given target concentration with an error in concentration factor less than [1/(2 n )]. To implement the algorithm, we design an architectural layout of a DMF-based LoC consisting of two O ( n )-size rotary mixers and O ( n ) storage electrodes. Simulation results show that the proposed technique always yields nonnegative savings in the number of waste droplets and also in the total number of input droplets compared to earlier methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12/2010; · 1.27 Impact Factor
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ABSTRACT: In nanometer ICs, when several transistors in physical proximity switch within the same clock cycle, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. Transistors may slow down because of lower supply voltage. Modelling of such timing faults, termed as droop faults, and their impact on the functionality and timing behaviour of the circuit are yet to be fully understood. In this study, a simple automatic test pattern generation (ATPG) based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits and full scan sequential circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 and ISCAS-89 benchmark circuits reveal that a very high droop fault coverage can be obtained by applying a short sequence of test vectors.
IET Computers & Digital Techniques 08/2010; · 0.45 Impact Factor
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ABSTRACT: The double-tree scan-path architecture, originally proposed for low test power, is adapted to simultaneously reduce the test application time and test data volume under external testing. Experimental results show significant performance improvements over other existing scan architectures.
VLSI Design, 2010. VLSID '10. 23rd International Conference on; 02/2010
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ABSTRACT: Automatic cell sorting and isolation for recovery of such live cells, mostly microorganisms, is a challenging task. Lab-on-a-chip devices implemented as cell arrays are used for this purpose. For an abstract model of the problem, we can assume the cell array to be represented by a matrix where each cell can be any of the three types: empty, good (or desired) and bad (or undesired). The problem is to separate the good and the bad cells by pushing them under electric field to their respective receptors at the corners of the cell array. We address some combinatorial optimization problems related to this biological phenomenon.
Nature & Biologically Inspired Computing, 2009. NaBIC 2009. World Congress on; 01/2010
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ABSTRACT: Matching and analysis of patterns or shapes in the digital plane are of utmost importance in various problems of computer vision and pattern recognition. A digital point set is such a pattern that corresponds to an object in the digital plane. Although there exist several data structures that can be employed for Approximate Point Set Pattern Matching (APSPM) in the real domain, they require substantial modification to support algorithms in the digital domain. To bridge this gap, a novel data structure called "angular treerdquo is proposed, targeting an efficient and error-controllable circular range query in the digital plane. The farthest pair of points may be used as the starting correspondence between the pattern set and the background set. Several classical discrete structures and methodologies of computational geometry, as well as some topological features of circles/discs in digital geometry, have been used in tandem, for successful realization of the proposed APSPM algorithm in the digital plane. The APSPM algorithm based on the angular tree has been implemented and tested on various point sets and the reported results demonstrate the efficiency and versatility of the new data structure for supporting APSPM algorithms.
IEEE Transactions on Pattern Analysis and Machine Intelligence 06/2009; · 4.91 Impact Factor
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ABSTRACT: In nanometer-scale integrated circuits, simultaneous switching at gates in physical proximity may induce power supply droop, and thereby invoke timing faults, termed as droop faults. During at-speed testing of such chips, two test vectors in a test sequence may excite droop and, thus, cause test invalidation. Fast application of test vectors may be needed for high-speed testing or for built-in self-test systems. The occurrence of droop strongly depends on the sequence of test vectors applied. The effect of droop on fast testing of stuck-at faults is investigated. For combinational circuits, the droop sensitivity of a given test sequence is studied and a method of re-ordering to reduce this effect is proposed. Experimental results on benchmark circuits show that the increase in test length to achieve droop-insensitive re-ordering is low. Droop excitability in full-scan sequential circuits is also studied.
IET Computers & Digital Techniques 04/2009; · 0.45 Impact Factor
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ABSTRACT: Efficient technology mapping has become an important vehicle in deep-submicron technologies for improving performance-oriented synthesis. On the other hand, library-based Pass Transistor Logic (PTL) synthesis, like Lean Integration with Pass-Transistors (LEAP) synthesis, has drawn significant attention to the VLSI research community. In this paper, we propose three new library cells based on differential cascode voltage Switch with Pass Gate Logic (DCVSPG). Synthesis using these cells outperforms the existing LEAP-based synthesis for BDD-based (Binary Decision Diagram-Based) circuits. Results on benchmark circuits show that the new cell-based mapping technique yields more than 60% reduction in both power and delay in the synthesized circuits.
Design and Test Workshop, 2008. IDT 2008. 3rd International; 01/2009
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ABSTRACT: This paper describes a new adaptive built-in self-test (BIST) technique for detecting stuck-open faults in a CMOS complex cell. A test pattern generator (TPG) that adaptively generates a sequence of single-input-change test pairs based on the past responses of the circuit under test (CUT) is designed. Conventional TPGs produce a predefined sequence of test vectors. The novelty of the proposed approach lies in the fact that the test sequence (TS) generated by the TPG depends on the actual error produced by the CUT during testing. The BIST design is universal, i.e., independent of the structure or functionality of the CUT, and depends only on the number of inputs to the CUT. The length of the TS (|TS|) also depends on the error behavior; hence, it significantly reduces the average test application time. For an n -input CUT, it is shown that 4 les |TS | les 2 n ldr2<sup>n</sup>. The design of the response analyzer is also simple. Barring a few exceptions, any irredundant multiple stuck-open faults, including those simultaneously occurring in both the n - and p - parts of a complex cell, are guaranteed to be detected using the proposed BIST scheme.
IEEE Transactions on Instrumentation and Measurement 01/2009; · 1.21 Impact Factor
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ABSTRACT: A new technique of synthesizing totally symmetric Boolean
functions is presented that achieves complete robust path-delay fault
testability. We show that every consecutive symmetric function can be
expressed as a logical composition (e.g., AND, NOR) of two unate
symmetric functions, and the resulting composite circuit can be made
robustly path-delay fault testable, if the constituent unate functions
are synthesized as two-level irredundant circuits. Nonconsecutive
symmetric functions can also be synthesized by decomposing them into a
set of consecutive symmetric functions. The circuit cost of the proposed
design can further be reduced by a novel algebraic factorization
technique based on some combinatorial clues. The overall synthesis
guarantees complete robust path-delay fault testability, and can be
completed in linear time. The results shows that the proposed method
ensures a significant reduction in hardware, as well as in the number of
paths, which in turn, reduces testing time, as compared to those of the
best-known earlier methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10/2000; · 1.27 Impact Factor
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ABSTRACT: A new technique of synthesizing symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit will be 100% robustly path-delay fault testable, if the constituent unate functions are synthesized with two-level irredundant circuits. Non-consecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The hardware overhead of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results reveal that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn reduces testing time as compared to those of the best known earlier methods
VLSI Design, 1999. Proceedings. Twelfth International Conference On; 02/1999
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ABSTRACT: A novel approach to the classical single-row routing problem is
presented. The approach is based on a graph-theoretic representation, in
which an instance of the single row routing problem is represented by
three graphs: a circle graph, a permutation graph, and an interval
graph. Three schemes for decomposition of the problem are presented. The
decomposition process is applied recursively until either each
subproblem is nondecomposable or it belongs to one of the special
classes of single row routing problem. For some special classes, it is
shown that routing can be done optimally, while solution in other cases
can be approximated using heuristic algorithms. These solutions of
subproblems are then combined to obtain the solution of the given
problem
Circuits and Systems, 1988., IEEE International Symposium on; 07/1988
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ABSTRACT: In the paper we investigate whether the function-independent test set for detecting single stuck-at faults in networks realising Reed-Muller canonic (RMC) expansions of switching functions is sufficient to detect all bridging faults in such networks. The investigation, however, reveals its insufficiency, and to circumvent this we propose a technique of augmenting the network with some additional observation points, so that a universal test set can be designed for detecting bridging faults as well.
Computers and Digital Techniques, IEE Proceedings E. 06/1985;
