[Show abstract][Hide abstract] ABSTRACT: This paper discusses the fundamental challenges and reports the recent progress in enabling embedded Si:C (eSi:C) nMOS source/drain stressor technology. A thick oxide (SiON, Toxgl ~ 26Aå) long channel (Lgate in the range of 80nm-110nm, gate-pitch =336nm) nMOS device was used as the main test structure to evaluate the impact of eSi:C stressor to the device electrical characteristics, such as channel mobility and drive current. It was demonstrated that modifying the conventional Si CMOS fabrication process to accommodate the intrinsically meta-stable eSi:C material property is crucial in keeping carbon in its substitutional site thus to preserve strain in the eSi:C stressor throughout the device fabrication process. Significant channel mobility and drive current enhancement was demonstrated in the thick-oxide long-channel nMOS devices using in situ phosphorus-doped (ISPD) epitaxial eSi:C source/drain material.
[Show abstract][Hide abstract] ABSTRACT: In addition to device scaling, strain engineering using SiC stressors in the S/D regions is important for nFET performance enhancement. In this paper, we review the characterization of fully-strained epitaxial SiC and in-situ doped SiC:P films for various ion implant conditions and anneals that are typically used in traditional CMOS flows. Full characterization has helped identify process integration schemes which give significant drive current enhancements.
[Show abstract][Hide abstract] ABSTRACT: We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (C<sub>sub</sub>) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced I<sub>eff</sub> and ~15% improved I<sub>dlin</sub> against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.
[Show abstract][Hide abstract] ABSTRACT: This work demonstrates that the ~2times mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress. (110) PMOS with 3.5 GPa compressively stressed liners demonstrate strong channel drives with I<sub>on</sub>=800 muA/mum at I<sub>off</sub>=100 nA/mum (V<sub>dd</sub>=10 V) for 190 nm poly-pitch, the highest reported to date for 45-nm-node (110) PMOS using conventional gate dielectrics without eSiGe stressors. Additionally, (110) PMOS show better scalability, with 15% smaller total I<sub>on</sub> degradation than (100) PMOS when poly-pitch scales from 250 nm to 190 nm.