A Ohta

Publications (2)0 Total impact

• Conference Proceeding: Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate

  M. Kadoshima, T. Matsuki, M. Sato, T. Aminaka, E. Kurosawa, A. Ohta, H. Yoshinaga, S. Miyazaki, K. Shiraishi, K. Yamabe, K. Yamada, T. Aoyama, Y. Nara, Y. Ohji
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  ABSTRACT: We propose a new dual-metal-gate dual-high-k CMOS integration technology using TaSiN gate HfSiON n-FET and TiAIN gate HfAlSiON p-FET for hp 32 nm low standby power (LSTP) CMOS devices. Low V, of p-FET, namely high effective work function of 4.8 eV was obtained due to spontaneous AIN-cap formation of TiAIN and subsequent intermixing between AIN-cap and HfSiON by high temperature annealing. There was no degradation in gate leakage current and electron mobility in TaSiN gate HfSiON n-FET even if TaSiN was formed after TiAIN removal. Thus, this technique is practical for realizing dual-metal-gate dual-high-k CMOS devices.
  Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
• Conference Proceeding: Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS

  M. Kadoshima, Y. Sugita, K. Shiraishi, H. Watanabe, A. Ohta, S. Miyazaki, K. Nakajima, T. Chikyow, K. Yamada, T. Aminaka, E. Kurosawa, T. Matsuki, T. Aoyama, Y. Nara, Y. Ohji
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  ABSTRACT: We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flatband voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n-and p-FET but they are automatically converted into dual high-k after the annealing process.
  VLSI Technology, 2007 IEEE Symposium on; 07/2007