-
[show abstract]
[hide abstract]
ABSTRACT: This letter reports the impact of surface morphology on the carrier transport and radio-frequency performance of graphene FETs formed on epitaxial graphene synthesized on SiC substrates. Such graphene exhibits long terrace structures with widths between 3-5 μm and steps of 10 ± 2 nm in height. While a carrier mobility value above 3000 cm<sup>2</sup>/V·s at a carrier density of 10<sup>12</sup> cmx<sup>2</sup> is obtained in a single graphene terrace, the step edges can result in a step resistance of ~21 kΩ·μm. By orienting the transistor layout so that the entire channel lies within a single graphene terrace and by reducing the access resistance associated with the ungated part of the channel, a cutoff frequency above 200 GHz is achieved for graphene FETs with channel lengths of 210 nm, i.e., the highest value reported on epitaxial graphene thus far.
IEEE Electron Device Letters 11/2011; · 2.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: High-performance graphene field-effect transistors are fabricated on two-inch graphene-on-SiC wafers. Epitaxial graphene was synthesized on SiC wafers by thermal annealing to form one to two layers of graphene. The graphene transistors possess high current density of >; 1mA/μm, and a cutoff frequency of 170 GHz is achieved for graphene FETs with a gate length of 90 nm. These results unravel the great potential of graphene for future RF applications.
Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International; 07/2011
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, the authors present experimental studies on transport characteristics of graphene FETs with channel lengths down to 70 nm. The factors limiting the performance of short channel graphene devices are discussed. RF performance of a sub-100 nm graphene transistor fabricated on epitaxial graphene grown on a SiC substrate is also presented. A cut-off frequency as high as 170 GHz is achieved in a 90 nm graphene FET using a scalable top-down fabrication processes. Our results indicate that further improvement of RF performance of graphene FETs can be enabled by channel length scaling with structure optimization and contact resistance reduction.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
-
[show abstract]
[hide abstract]
ABSTRACT: A detailed study of Through-Silicon-Vias (TSV) electrical properties is presented. A basic test structure is a dual-TSV made of tungsten TSVs based on hybrid copper-adhesive wafer bonding. Three measurement techniques are utilized: low frequency TSV capacitance characterization using an LCR meter; inductance extraction from the reflection coefficient of TSV chains; TSV frequency dependent capacitance using transmission line characterization method. Experimental results are in agreement with simulation data for each of the techniques. Furthermore, eye diagram and RLC evaluation show the utility of the dual-TSV for highperformance 3DI system applications.
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th; 07/2010
-
[show abstract]
[hide abstract]
ABSTRACT: A dual-gate graphene field-effect transistor is presented, which shows improved radio-frequency (RF) performance by reducing the access resistance using electrostatic doping. With a carrier mobility of 2700 cm<sup>2</sup>/V ?? s, a cutoff frequency of 50 GHz is demonstrated in a 350-nm-gate-length device. This f<sub>T</sub> value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOS field-effect transistors at the same gate length, illustrating the potential of graphene for RF applications.
IEEE Electron Device Letters 02/2010; · 2.85 Impact Factor
-
ECS TRANSACTIONS; 01/2010
-
[show abstract]
[hide abstract]
ABSTRACT: When VLSI circuits operate at multi-GHz frequencies, the demand for precise clock generation and distribution become more
and more stringent. Inevitably, clock edges develop timing jitter, which is the deviation of the timing of the clock edges
from their ideal values. Jitter arises from power supply noise on the circuits which distribute the clock, and from the phase-locked
loops (PLLs) which generate a high frequency clock by multiplying a very stable lower frequency signal. Since computation
requires that certain logical operations are completed within each clock cycle, a certain amount of jitter is assumed in the
design of a chip, by including it in the clock budget. Jitter which is too large can impact the allowed clock budget, or even
cause data transmission and computation errors. The measurement of jitter is required for high-speed circuits, to determine
if timing specifications and margins are met. In contemporary circuits, where clock periods may be as small as 250 or 300
ps, rms jitter may be required to be as small as a few picoseconds. Conventional measurement of such small timing delays requires
driving the signal of interest off-chip with high fidelity off chip drivers. Measurement is performed with a high performance
oscilloscope or similar instrument, limiting characterization to only a few samples.
12/2009: pages 203-217;
-
[show abstract]
[hide abstract]
ABSTRACT: The pronounced impact of process uncertainties on the power-performance characteristics of systems has necessitated characterization and design efforts that aim to maximize the parametric yield of the design. This paper describes a completely digital on-chip technique to measure local random variation of FET current. The measurement circuit consists of a series connection of an array of independently selectable devices and a single common load device. The voltage at the intermediate node indicates the variation from device to device, and is digitized by a voltage-controlled oscillator and on-chip frequency counters. This eliminates analog current measurements and enables very rapid, all-digital measurement of single FET variability, which can also be carried out in the field. The effectiveness of the technique is illustrated using measurements results from a test chip designed in a 45-nm SOI process.
IEEE Journal of Solid-State Circuits 10/2009; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse-probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ~50 mK, a time resolution of 5 ns, and a temperature sensitivity of ~0.6 muA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental-simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail.
IEEE Transactions on Electron Devices 08/2008; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurements.
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on; 07/2008
-
[show abstract]
[hide abstract]
ABSTRACT: This paper presents a completely on-chip digital circuit to measure local threshold-voltage variation using an array of identical devices under test (DUTs) stacked with a single reference device. This technique detects on-chip variation of single devices, rather than matched device pairs or SRAM cells. The variation in V<sub>t</sub> of the DUTs is detected as variation in frequency, measured by on-chip counters, resulting in a simple digital measurement. The circuit is implemented in NMOS and PMOS versions. The standard deviation of local threshold variation measured on a chip-to-chip basis on a full wafer. The results indicate that the test-structure estimates local random mismatch in MOS current (and threshold voltage) with a small time and complexity, and thus enable technology optimization and yield improvement.
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we report the first resolving detailed thermal transients for CMOS devices. Furthermore we investigate different heat paths between and inside devices to reveal the importance of the thermal conductivity of the gate. This work is extended to study thermal transport within a sub-micrometer CMOS FET where we are able to detect the delayed heat pulse at the source due to heat generation in the drain. We show both by measurements and simulations that oxide does not afford good isolation and that the main cooling mechanism of SOI devices is to the gate, with transfer resistance playing an important role.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
-
[show abstract]
[hide abstract]
ABSTRACT: A circuit for on-chip measurement of period jitter and skew of clock distribution is described. The circuit uses a single latch and a voltage-controlled delay element. The circuit is evaluated in a stand-alone pad frame, where a jitter resolution of about 1 ps is demonstrated, and is incorporated in a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurement.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
-
[show abstract]
[hide abstract]
ABSTRACT: Ultrahigh performance fully depleted nMOSFETs have been fabricated on ultra-thin silicon-on-insulator (UTSOI) with a body thickness of 18 nm and channel lengths down to 20 nm. Uniaxial tensile stress induced in the channel using stressed contact liners and stress memorization was found to significantly improve ac performance, resulting in cutoff frequencies f<sub>t</sub> as high as 330 GHz. This is the highest f<sub>T</sub> value reported on fully depleted UTSOI MOSFETs and is among the highest f<sub>T</sub> values for any Si-based field-effect transistor. Stress memorization and stressed contact liners were found to have little impact on gate to source capacitance indicating that the enhancement in f<sub>T</sub> results primarily from stress-induced enhancements in transconductance.
IEEE Electron Device Letters 04/2006; · 2.85 Impact Factor
-
D.V. Singh,
J.W. Sleight,
J.M. Hergenrother,
Z Ren, K.A. Jenkins,
O. Dokumaci,
L. Black,
J.B. Chang,
H Nakayama,
D. Chidambarrao,
R. Venigalla,
J. Pan,
W. Natzle,
B.L. Tessier,
A Nomura,
J.A. Ott,
M. Ieong,
W. Haensch
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
-
[show abstract]
[hide abstract]
ABSTRACT: A circuit for accurate on-chip measurement of timing jitter is demonstrated. Measurements with the circuit show excellent reproduction of corresponding off-chip measurements made with an oscilloscope, and resolution measurements show the jitter resolution of the circuit to be better than 0.4 ps rms. The circuit is very compact, occupying 3200 μm<sup>2</sup> in a 0.13μm, 1.2V, CMOS technology, and operates up to 2.5 GHz in this technology.
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European; 10/2005
-
J. U. Knickerbocker,
P. S. Andry,
L. P. Buchwalter,
A. Deutsch,
R. R. Horton, K. A. Jenkins,
Y. H. Kwark,
G. McVicker,
C. S. Patel,
R. J. Polastre,
C. D. Schuster,
A. Sharma,
S. M. Sri-Jayantha,
C. W. Surovic,
C. K. Tsang,
B. C. Webb,
S. L. Wright,
S. R. McKnight,
E. J. Sprogis,
B. Dang
[show abstract]
[hide abstract]
ABSTRACT: System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a “virtual chip” using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.
Ibm Journal of Research and Development 08/2005; · 0.72 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to mitigate the problems encountered in trying to implement architectures employed in conventional stand-alone instruments on a chip. Specifically, it makes use of a very-low IF architecture, which leads to a highly compact design, that can be used for measuring the frequency content of high frequency on-chip signals. The architecture and design considerations along with an implementation in a 0.18 μ CMOS process is described. The design takes up an area of approximately 0.384 mm<sup>2</sup> with a simulated frequency range of 33 MHz to 3 GHz and a dynamic range of 60 dB.
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE; 06/2005
-
[show abstract]
[hide abstract]
ABSTRACT: The frequency response of a carbon nanotube field effect transistor (CNFET) biased in the common-source and common-gate configurations has been measured up to 200 MHz for the first time using a direct measurement technique. In this frequency range there is no observed degradation in the measured AC response of the CNFET. The effect of parasitic capacitance on the measurement has been identified and based on a simple model; it is estimated that this approach can be extended well into the Gigahertz range. This is the only demonstrated method of directly characterising the frequency response of nanoscale devices where the signal levels are below the noise floor of conventional network analysers.
Electronics Letters 04/2005; · 0.96 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We report on the dc and RF characterization of laterally scaled, Si-SiGe n-MODFETs. Devices with gate length, L<sub>g</sub>, of 80 nm had f<sub>T</sub>=79 GHz and f<sub>max</sub>=212 GHz, while devices with L<sub>g</sub>=70 nm had f<sub>T</sub> as high as 92 GHz. The MODFETs displayed enhanced f<sub>T</sub> at reduced drain-to-source voltage, V<sub>ds</sub>, compared to Si MOSFETs with similar f<sub>T</sub> at high V<sub>ds</sub>.
IEEE Electron Device Letters 04/2005; · 2.85 Impact Factor
