K.A. Jenkins

IBM, Armonk, New York, United States

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Publications (215)367.46 Total impact

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    ABSTRACT: This paper analyzes the root cause of performance degradation and the impact of hot-carrier injection (HCI) on the lifetime prediction of an $LC$ voltage-controlled oscillator (LC-VCO). Observed from both constant voltage stress and ramped voltage stress tests, it is shown that the dominant degradation mechanism shifts from a negative bias temperature instability to an HCI due to the accelerated aging condition. Furthermore, simulations show that a frequency increase of degraded VCO is mainly attributed to the degradation in the pMOSFET of a cross-couple pair, while the degradations in the pMOSFET and nMOSFET have relatively the same impact on the startup voltage shift. Compared with the frequency change, the degradation of the startup voltage of an $LC$-VCO is less sensitive to device width. Based on the observed results, methodologies to optimize the reliability tests and mitigate the frequency shift of LC-VCO are proposed.
    IEEE Transactions on Electron Devices 07/2015; 62(7):1-1. DOI:10.1109/TED.2015.2436905 · 2.47 Impact Factor
  • Pong-Fei Lu · Keith A. Jenkins · Tobias Webel · Oliver Marquardt · Birgit Schubert ·
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    ABSTRACT: Long-term measurement of bias temperature instability (BTI) degradation obtained from an on-chip sensor is presented. The sensor reports measurements periodically with a digital output. Implemented on IBM’s z196 enterprise systems using IBM 45 nm technology, it can be used to monitor long-term degradation under real-use conditions. Over 700 days worth of ring oscillator degradation data from customer systems is presented. The data obtained by this sensor are consistent with models based on accelerated testing.
    Microelectronics Reliability 07/2014; 54(11). DOI:10.1016/j.microrel.2014.06.016 · 1.43 Impact Factor
  • Chih-Hsiang Ho · Keith A. Jenkins · Herschel Ainspan · Emily Ray · Peilin Song ·
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    ABSTRACT: This paper presents a comprehensive study of the impact of Hot Carrier Injection (HCI) on differential LC Voltage Controlled Oscillator (VCO) reliability tests. Although Negative Bias Temperature Instability (NBTI) has been recognized as major cause for reliability degradation of advanced circuits, HCI-induced degradation may become significant due to the accelerated aging of reliability tests leading to incorrect circuit lifetime prediction. To distinguish HCI effects, different stress voltages and frequencies are applied in Constant Voltage Stress (CVS) and Ramp Voltage Stress (RVS) tests. It is verified that the stress voltage and frequency dependence of time and voltage exponents in the reliability tests are due to the effect of HCI. Based on the observed results, a methodology is proposed to define proper stress conditions for accelerated circuit reliability tests for better lifetime prediction.
    2014 IEEE International Reliability Physics Symposium (IRPS); 06/2014
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    ABSTRACT: Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.
    Nature Communications 01/2014; 5:3086. DOI:10.1038/ncomms4086 · 11.47 Impact Factor
  • Tony Tae-Hyoung Kim · Pong-Fei Lu · Keith A. Jenkins · Chris H. Kim ·
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    ABSTRACT: Ring-oscillator-based test structures that can separately measure the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) degradation effects in digital circuits are presented for high-k metal gate devices. The mathematical derivation also shows that the structure for frequency degradation measurement can directly be used for estimating the portion of the NBTI and PBTI in the conventional ring oscillator. The proposed test structures including frequency degradation sensing circuitry have been implemented in an experimental high-k/metal gate SoI process.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2014; 23(7):1-1. DOI:10.1109/TVLSI.2014.2339364 · 1.36 Impact Factor
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    ABSTRACT: With the rapid advances in graphene field-effect transistor (GFET) performances, graphene has attracted much interest as a future channel material in RF electronics. However, the pace of the development of graphene circuits seems significantly slower. Several graphene circuits demonstrated today showing promising GHz functions still relied on ideal discrete passive components connected at the equipment level, and these circuits are limited to single transistor designs [1-3]. To compete with existing technologies requires that all active and passive components be monolithically integrated for not only the small circuit footprint and low cost but also high circuit complexity and advanced system functionality.
    2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
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    ABSTRACT: Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.
    IEEE Transactions on Components, Packaging, and Manufacturing Technology 11/2013; 3(11):1917-1925. DOI:10.1109/TCPMT.2013.2264755 · 1.18 Impact Factor
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    ABSTRACT: The linearity of the radio frequency response of graphene field-effect transistors has been measured as a function of gate bias using the two-tone method. Two kinds of transistors, which differ in both the graphene source material and the device structure, have been compared. Both devices show high linearity compared to contemporary silicon transistors. The physical origins of this behavior are analyzed and discussed.
    Applied Physics Letters 10/2013; 103(17):173115. DOI:10.1063/1.4826932 · 3.30 Impact Factor
  • Shu-Jen Han · Satoshi Oida · Keith A. Jenkins · Darsen Lu · Yu Zhu ·
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    ABSTRACT: Gate resistance plays a key role in determining the maximum oscillation frequency (f(MAX)) of all radio frequency transistors. This letter presents a new graphene device structure having multiple-finger T-shaped gates embedded in the substrate. The structure possesses several advantages over conventional top gate structures, including low gate resistance, low parasitic capacitance, scalable gate dielectric, and simple interconnect wiring. With 1 V drain bias, f(MAX) up to 20 GHz, and similar to 25%-43% higher than the current gain cutoff frequency (f(T)), is achieved from devices with a channel length down to 250 nm.
    IEEE Electron Device Letters 10/2013; 34(10):1340-1342. DOI:10.1109/LED.2013.2276038 · 2.75 Impact Factor
  • Xiaoxiong Gu · Keith Jenkins ·
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    ABSTRACT: Substrate noise coupling in 3-D CMOS SOI technology is characterized using hardware measurement. Couplings between device contacts and through-silicon vias (TSVs) are measured in frequency domain. Time domain simulations based on the measured S-parameters are performed to assess the impact of TSV-induced noise coupling on active circuit performance. Equivalent circuits are constructed with good model-to-hardware correlation. The characterization results demonstrate a dominant noise-coupling path through N+ epi layer in the SOI substrate. The data also successfully validates our proposed noise mitigation technique of using CMOS process compatible buried interface contacts, e.g., achieving over 20-dB reduction for TSV-induced substrate noise coupling at 1 GHz.
    2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS); 10/2013
  • Keith A. Jenkins · Pong-Fei Lu ·
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    ABSTRACT: A circuit for on-chip monitoring bias-temperature instability (BTI) degradation of CMOS devices, which distinguishes between NBTI and PBTI, is described. Intended for long-term monitoring of field-installed systems, the measurements are performed entirely on chip, and reported through digital scan chains. The circuit measures the frequency degradation of conventional inverters, and separately measures the degradation due only to NBTI and only to PBTI. The measurement time is very short compared to off-chip measurements. The operation of the circuit is demonstrated with examples from polysilicon gate technology and high-k/metal-gate technology.
    Microelectronics Reliability 09/2013; 53(9-11):1252-1256. DOI:10.1016/j.microrel.2013.07.039 · 1.43 Impact Factor
  • Wenjuan Zhu · Tony Low · Damon B. Farmer · Keith Jenkins · Bruce Ek · Phaedon Avouris ·
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    ABSTRACT: The excellent electrical properties of graphene, such as its high carrier mobility, gate tunability, and mechanical flexibility makes it a very promising material for radio frequency (RF) electronics. Here we study the impact of top and bottom gate control on the essential performance metrics of graphene RF transistors. We find that the maximum cut-off frequency improves as the bottom gate voltage is tuned towards the same polarity as the top gate bias voltage. These results can be explained by the bottom-gate tunable doping of the graphene underneath the metal contacts and in the under-lap region. These effects become more dramatic with device down-scaling. We also find that the minimum output conductance occurs, when the drain voltage roughly equals an effective gate voltage (Veff ≈ VTG+VBG⋅CBG/CTG, where VTG and VBG are top and bottom gate voltage, CTG and CBG are the respective gate capacitance). The minimum output conductance is reduced as the bottom gate bias increases, due to the stronger control of the channel from the bottom gate, lessening the influence of the drain voltage on the drain current. As a result of these two influences, when the bottom gate voltage is tuned towards the same polarity as the top gate voltage, both the maximum oscillation frequency (fmax) and the intrinsic gain significantly improve. The intrinsic gain can increase as high as 3–4 times as the gain without the bottom gate bias. Tuning the bottom gate to enhance fmax and gain will be very important elements in the effort to enable graphene RF devices for practical use.
    Journal of Applied Physics 07/2013; 114(4). DOI:10.1063/1.4816443 · 2.18 Impact Factor
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    ABSTRACT: Graphene is a very promising candidate for applications in flexible electronics due to its high carrier mobility and mechanical flexibility. In this paper, we present results on graphene RF devices fabricated on polyimide substrates with cutoff frequencies as high as 10 GHz. Excellent channel mobility and current saturation are observed in graphene long channel devices on polyimide. Graphene devices on polyimide also show very good temperature stability from 4.4 K to 400 K and excellent mechanical flexibility up to a bending radius of 1 mm. These demonstrated properties make graphene an excellent candidate for flexible wireless applications.
    Applied Physics Letters 06/2013; 102(23). DOI:10.1063/1.4810008 · 3.30 Impact Factor
  • Shu-Jen Han · Satoshi Oida · Keith A. Jenkins · Darsen D. Lu ·
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    ABSTRACT: Remarkable progress has been made in both graphene RF transistor level [1] and the circuit level [2]. Despite the demonstrated high current gain cutoff frequency (fT), most devices also show significantly lower maximum oscillation frequency (fMAX), which is a crucial figure of merit that really determines the device performance in most RF circuits. It is well known that gate resistance (Rg) plays a key role in deciding fMAX, and T-shaped gate structures have been adopted in semiconductor industries for very high-speed RF transistor designs by maximizing the cross-sectional area of the gate. This paper presents an embedded T-gate graphene FET structure. With merely 1 V drain bias, extrinsic fMAX up to 20 GHz, and about 25% to 55% higher than fT, is achieved from devices with a channel length down to 250 nm. Besides the same key advantage of the embedded gate - bypassing the use of seed layers for obtaining ultra-high quality gate dielectrics [3], this new structure also provides uncomplicated process flow, low parasitic capacitance, and simple circuit wiring.
    2013 71st Annual Device Research Conference (DRC); 06/2013
  • Wenjuan Zhu · Damon Farmer · Yanqing Wu · Bruce Ek · Keith Jenkins · Phaedon Avouris ·
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    ABSTRACT: Graphene is very promising for RF devices due to its high carrier mobility. High cut-off frequency graphene RF devices using CVD grown graphene and epitaxially grown graphene have been reported. Here we report the effect of the back-gate bias on the FET cut-off frequency and current saturation. We found that there are two peak cut-off frequencies corresponding to electron peak trans-conductance and hole peak trans-conductance maxima respectively, as we sweep the top-gate bias. The electron peak cut-off frequency can be significantly increased by applying a positive back-gate bias. The higher the voltage, the larger the maximum cut-off frequency. This can be explained by the additional electron doping introduced by the back-gate bias in the under-lap region, which forms an n-n+-n configuration. Similarly, the hole peak cut-off frequency can be significantly enhanced by applying negative back-gate bias to form the p-p+-p configuration. The shorter the channel, the more pronounced this effect. We also found that the current saturation is also improved by introducing the same type of carrier as the channel in the under-lap region.
  • Pong-Fei Lu · K.A. Jenkins ·
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    ABSTRACT: A circuit for long-term measurement of bias temperature instability (BTI) degradation is described. It is an entirely on-chip measurement circuit, which reports measurements periodically with a digital output. Implemented on IBM's z196 Enterprise systems, it can be used to monitor long-term degradation under real-use conditions. Over 500 days worth of ring oscillator degradation data from customer systems are presented. The importance of using a reference oscillator to measure performance degradation in the field, where the supply voltage and temperature can vary dynamically, is shown.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: This work presents recent advances in the development of graphene technology for various applications from RF to THz frequencies. First, large-scale graphene synthesis methods are reviewed. Graphene FETs suitable for RF applications are then presented along with their DC and RF characteristics. The challenges and current progress toward wafer-scale integration of graphene-based RFICs are also discussed including RFIC measurement results up to 200C. Finally, the absorption properties of graphene at THz frequencies are discussed.
    Microwave Symposium Digest (IMS), 2013 IEEE MTT-S International; 01/2013
  • K.A. Jenkins · P. Restle · P.Z. Wang · D. Hogenmiller · D. Boerstler · T. Bucelot ·
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    ABSTRACT: An on-chip circuit to measure full analog waveforms of internal signals is described. It can measure signals up to a repetition rate of at least 7 GHz, a bandwidth of at least 12 GHz, with accuracy required to detect subtle differences in signals, and it can measure overshoot above the rail voltage. It has been demonstrated on an experimental clock grid with optional resonant operation.
    VLSI Test Symposium (VTS), 2013 IEEE 31st; 01/2013
  • J.B. Kuang · K.A. Jenkins · K. Stawiasz · J. Schaub ·
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    ABSTRACT: A compact SRAM ring oscillator circuit for local, in-situ, probing of device performance is described. Applied to three-dimensional integrated circuit technology (3DI), the circuit is used to determine if there is any effect on SRAM performance when the cells are placed in close proximity to through-silicon vias (TSVs).
    ESSCIRC (ESSCIRC), 2013 Proceedings of the; 01/2013
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    ABSTRACT: We report the radio-frequency performance of carbon nanotube array transistors that have been realized through the aligned assembly of highly separated, semiconducting carbon nanotubes on a fully scalable device platform. At a gate length of 100 nm, we observe output current saturation and obtain as-measured, extrinsic current gain and power gain cut-off frequencies, respectively, of 7 GHz and 15 GHz. While the extrinsic current gain is comparable to the state-of-the-art the extrinsic power gain is improved. The de-embedded, intrinsic current gain and power gain cut-off frequencies of 153 GHz and 30 GHz are the highest values experimentally achieved to date. We analyze the consistency of DC and AC performance parameters and discuss the requirements for future applications of carbon nanotube array transistors in high-frequency electronics.
    Applied Physics Letters 08/2012; 101(5). DOI:10.1063/1.4742325 · 3.30 Impact Factor