O. Flament

Cea Leti, Grenoble, Rhône-Alpes, France

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Publications (72)68.24 Total impact

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    ABSTRACT: A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given “critical” dose. Above this dose, we still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic conduction is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies
    IEEE Transactions on Nuclear Science 01/1999; · 1.22 Impact Factor
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    ABSTRACT: Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. We present, here, a new method to measure and analyse this effect together with a simple model. We also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. We show that it explains some of the upsets observed in a SRAM embedded in an ASIC
    IEEE Transactions on Nuclear Science 07/1998; · 1.22 Impact Factor
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    ABSTRACT: This work concerns the development of a methodology specially devoted to lateral parasitic transistors that limit the total dose hardness of CMOS technologies. This methodology is based on i) the irradiation of standard NMOS transistors followed by ii) isochronal annealing measurements to determine energetic spectra of the field oxide trapped charge. Post irradiation effects have been evaluated through additional isothermal annealing experiments at 75°C which are consistent with isochronal results. We propose a test procedure which allows to determine physical parameters helpful to improve comparison and qualification Of CMOS commercial technologies
    IEEE Transactions on Nuclear Science 07/1998; · 1.22 Impact Factor
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    ABSTRACT: Capacitance-voltage and thermally-stimulated-current techniques are used to estimate trapped hole and electron densities in MOS oxides as functions of irradiation and isochronal anneal temperature. Trapped-charge annealing and compensation effects are discussed.
    01/1998
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    ABSTRACT: In this work, the evolution of the oxide trapped charge has been modeled, to predict post-irradiation behavior for arbitrary anneal conditions (i.e. arbitrary temperature-time profiles). Using experimental data obtained from a single isochronal anneal, the method consists of calculating the evolution of the energy distribution of the oxide trapped charge, in the framework of a thermally activated charge detrapping model. This methodology is illustrated in this paper by the prediction of experimental isothermal data from isochronal measurements. The implications of these results to hardness assurance test methods are discussed
    IEEE Transactions on Nuclear Science 01/1998; · 1.22 Impact Factor
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    ABSTRACT: We have performed current-voltage and charge pumping measurements on LOCOS parasitic transistors submitted to X-ray irradiation. The electrical behavior and the charge pumping response of these non-planar structures have been analyzed by two-dimensional computer simulations. We report how this experimental approach allows us to obtain quantitative information about oxide charge and interface trap densities in different parts of the complete structure. Our results show a maximum of oxide charge trapping and interface trap buildup in the bird's beak regions after irradiation. The generation of radiation-induced interface and border traps along the LOCOS SiO<sub>2</sub>/Si interface is discussed, in terms of trap density and frequency response
    IEEE Transactions on Nuclear Science 01/1998; · 1.22 Impact Factor
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    ABSTRACT: A method combining charge pumping and current-voltage measurements is presented for determining the surface potential versus gate voltage relationship in irradiated MOS transistors. This technique uses parameter optimization and simple numerical equations. It can be applied even for a high interface state density and for a non-uniform distribution in the silicon bandgap. This makes the method attractive for all studies concerning interface trap characterization or accurate modeling of MOS transistors in subthreshold regime. In this study, this new approach is applied to n-channel transistors irradiated up to 10 Mrad (SiO2)
    IEEE Transactions on Nuclear Science 01/1998; 45(3):1355-1364. · 1.22 Impact Factor
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    ABSTRACT: A method combining charge pumping and current-voltage measurements is presented for determining the surface potential versus gate voltage relationship in irradiated MOS transistors. This technique uses parameter optimization and simple numerical equations. It can be applied even for a high interface state density and for a non-uniform distribution in the silicon bandgap. This makes the method attractive for all studies concerning interface trap characterization or accurate modeling of MOS transistors in subthreshold regime. In this study, this new approach is applied to n-channel transistors irradiated up to 10 Mrad (SiO<sub>2</sub>)
    Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on; 10/1997
  • [Show abstract] [Hide abstract]
    ABSTRACT: Irradiation of insulators with a pulse of high energy X-rays can induce photocurrents in the interconnections of integrated circuits. We present, here, a new method to measure and analyse this effect together with a simple model. We also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. We show that it explains some of the upsets observed in a SRAM embedded in an ASIC
    Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on; 10/1997
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work concerns the development of a methodology specially devoted to lateral parasitic transistors that limit the total dose hardness of CMOS technologies. This methodology is based on i) the irradiation of standard NMOS transistors followed by ii) isochronal annealing measurements to determine energetic spectra of the field oxide trapped charge. Post irradiation effects have been evaluated through additional isothermal annealing experiments at 75°C which are consistent with isochronal results. We propose a test procedure which allows to determine physical parameters helpful to improve comparison and qualification of CMOS commercial technologies
    Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on; 10/1997 · 1.22 Impact Factor
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    ABSTRACT: This work concerns the development of a radiation hardness assurance methodology specially devoted to CMOS, JFET and bipolar transistors used in high total dose level environments. On the basis of recent studies, high temperature, high dose rate irradiations were performed. We propose a test procedure which combines high temperature irradiations and isochronal anneals for the qualification
    Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on; 10/1997 · 1.22 Impact Factor
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    ABSTRACT: We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors
    Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on; 10/1997
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    ABSTRACT: The trapped charge density in the LOCOS bird's beak resulting from irradiating a conventional NMOSFET has been analysed using a 2D finite element simulation. This paper shows a maximum of trapped charge density in the bird's beak region. The resulting voltage shift of the lateral parasitic transistor in the bird's beak region induces a high leakage current, and prevents any normal circuit operation. The silicon doping level, the supply voltage and the bird's beak shape are key parameters for device hardening of rad-tolerant technologies
    IEEE Transactions on Nuclear Science 01/1997; · 1.22 Impact Factor
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    ABSTRACT: Enhanced total dose damage of Junction Field-effect Transistors (JFETs) due to low dose rate and/or elevated temperature has been investigated for elementary p-channel structures fabricated on bulk and SOI substrates as well as for related linear integrated circuits. All these devices were fabricated with conventional junction isolation (field oxide). Large increases in damage have been revealed by performing high temperature and/or low dose rate irradiations. These results are consistent with previous studies concerning bipolar field oxides under low-field conditions. They suggest that the transport of radiation-induced holes through the oxide is the underlying mechanism. Such an enhanced degradation must be taken into account for low dose rate effects on linear integrated circuits
    IEEE Transactions on Nuclear Science 01/1997; · 1.22 Impact Factor
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    ABSTRACT: Different electrical characterization (subthreshold current-voltage measurements, 3-level and multi-frequency charge pumping) combined with isochronal anneals have been used to investigate the generation and the evolution of interface traps in radiation-hardened MOS transistors following exposure to 10 keV X-rays. The evolution of the interface state density (D<sub>it</sub>) during the anneal is found to be field-dependent and consistent with models involving a drift of positive species towards the Si-SiO<sub>2</sub> interface. The energy-resolved distributions of D<sub>it</sub> in the silicon bandgap show the emergence of two broad structures located at ~E <sub>V</sub>+0.35 eV and ~E<sub>V</sub>+0.75 eV immediately after irradiation and during the first steps of the isochronal anneal (up to ~175°C). At higher anneal temperatures, it is shown that the recovery of D<sub>it</sub> is not uniform in the two halves of the silicon bandgap. In particular, the separation of the D<sub>it</sub> distribution related to the lower part of the bandgap in two distinct peaks (at E<sub>V</sub>+0.30 eV and E<sub>V</sub>+0.45 eV) agrees well with the energy distributions of P<sub>b0</sub> and P<sub>b1</sub> centers. These results are consistent with Electron Spin Resonance (ESR) studies which have shown that P<sub>b</sub> centers play a dominating role in the interface trap build-up and recovery mechanisms. Since ESR measurements are only accurate to ~±30% in absolute number, P<sub>b</sub> centers do not probably account for all the electrically active interface trap defects, as also suggested by the evident asymmetry of the D<sub>it</sub> distributions in the bandgap. Finally, we investigate the post-irradiation response of border traps by reducing the charge pumping frequency to low values. The implication of these results on the nature of border traps is discussed
    IEEE Transactions on Nuclear Science 01/1997; · 1.22 Impact Factor
  • REE. Revue de l'électricité et de l'électronique. 01/1997;
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    ABSTRACT: An accelerated test method, combining different charge pumping techniques with isochronal anneals, has been used to investigate the generation and evolution of interface and border traps after uniform degradation (Fowler Nordheim injection and X-ray irradiation), simultaneously with their energy position in the silicon bandgap and their characteristic time constants.
    Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European; 10/1996
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    ABSTRACT: High Energy Physics experiments under preparation at CERN (Geneva, Switzerland) with the future LHC (Large Hadron collider) require a fast, low noise, very rad-hard, mixed analog-digital microelectronics VLSI technology. Readout electronics designed using such a technology for the central parts of the LHC particle detectors must withstand more than 10 Mrad (SiO<sub>2</sub>) and 10<sup>14</sup> neutrons/cm<sup>2</sup> over 10 years of operation. We present here recent results obtained with a new rad-hard analog-digital technology called DMILL, which monolithically integrates NPN bipolar, CMOS and P-JFET transistors, and which has been specifically developed to fulfill the severe constraints of LHC detector readout circuits
    IEEE Transactions on Nuclear Science 07/1996; · 1.22 Impact Factor
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    ABSTRACT: We describe transient effects induced by high energy protons in shift registers processed in a CMOS/thick SOI technology. Devices are tested in dynamic mode. The dependence of cross section on frequency, signal rise time, angle of incidence and proton energy is studied and interpreted
    IEEE Transactions on Nuclear Science 07/1996; · 1.22 Impact Factor
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    ABSTRACT: We have studied the sensitivity of a 256 Kbit CMOS/epi SRAM to transient phenomena (protons and ions SEU, dose rate). Local and global failure mechanisms are observed and discussed. For single particles, or at low dose rate, cell upsets are uncorrelated. When the dose rate is increased, correlated failures are due to both cell photocurrent summation (rail span collapse) and supply voltage drop in peripheral circuits. The transition between uncorrelated to correlated failures is interpreted, on the basis of device structure and pattern influence
    IEEE Transactions on Nuclear Science 07/1996; · 1.22 Impact Factor