R. Alini

University of Pavia, Ticinum, Lombardy, Italy

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Publications (13)10.23 Total impact

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    ABSTRACT: An eighth order linear phase continuous time low-pass filter implementing pulse shaping and noise filtering for partial response maximum likelihood (PRML) read channel applications is presented. The filter supports two operation modes: DATA and SERVO. In each mode the cutoff frequency is tunable in a 1 to 3 range for a fixed external reference resistor (a further 1 to 3.3 tuning range is available changing this resistor), the cutoff frequency range in SERVO is an half that in DATA. The amount of boost is programmable in the 6-15dB range for DATA and 3-9dB for SERVO. At the nominal signal swing of 100mVpp differential, the allowed distortion is 1%. The transconductance capacitance (Gm-C) filter is implemented in a 0.35µm 3.3V BiCMOS technology, occupies 0.14mm<sup>2</sup>and dissipates 46mW at 100MHz.
    Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European; 10/1999
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    ABSTRACT: A fully-integrated PRML read/write IC with digital adaptive FIR operating up to 450 Mbit/s is presented, The chip implements an EPR4 Viterbi detector as well as a digital servo. The device is integrated in a 0.35 μm BiCMOS technology, has a die size of 11.44 mm<sup>2</sup> (step and repeat) and dissipates 1.3 W (in read mode) at 450 Mbit/s
    Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999; 02/1999
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    ABSTRACT: A fully integrated partial response maximum likelihood (PRML) read/write IC with analog adaptive equalization operates up to 200 MSample/s. The chip implements both matched spectral null (MSN) trellis and standard PR4 Viterbi detectors in the digital domain as well as digital servo. The device is integrated in a mature 0.7-μm BiCMOS technology, has a die size of 54 mm<sup>2</sup>, and dissipates 2 W with MSN code or 1.5 W with PR4 code at 4.5-V supply and 200 MSample/s
    IEEE Journal of Solid-State Circuits 12/1997; · 3.06 Impact Factor
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    ABSTRACT: A fully-integrated R/W IC operates at 200 MSample/s channel rate and supports two recording codes: a rate 4/5 (0,4/8) matched spectral null (MSN) trellis code and associated detector, and a rate 8/9 (0,4/4) with a standard maximum-likelihood PR4 detector. The chip supports a complete flexible digital servo and four-level write precompensation to overcome media nonlinearity. The device is integrated in 0.7 μm BiCMOS technology, has 54 mm<sup>2</sup> die and uses 2 W with MSN code or 1.5 W with PR4 code at 4.5 V and 200 MSample/s. This chip avoids external interface chips, incorporating an ADC and functions useful to the servo DSP. MSN code provides approximately 2 dB gain in SNR with respect to rate 8/9 PR4 coding at a user density of PW<sub>50</sub>/T <sub>max</sub>=1.8
    Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International; 03/1997
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    ABSTRACT: This paper reports on a single-chip read/write channel for disk drive. The integrated circuit implements a peak detector architecture fully compatible with zoned-bit recording applications. The chip contains all the functions needed to implement a high performance read channel, i.e., pulse detector, programmable active filter, servo demodulator, frequency synthesizer, data separator and RLL(1,7) ENDEC. The design has been done in a way that takes full advantage of the features available in a BiCMOS technology to achieve power saving, high speed and immunity to cross-talk from digital to analog. The IC is fabricated in a 1.2 μ BiCMOS technology and has an active area of approximately 28 mm<sup>2</sup>. While operating from a single 5 V supply the power consumption is only 450 mW at 32 Mb/s
    IEEE Journal of Solid-State Circuits 07/1995; · 3.06 Impact Factor
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    ABSTRACT: A design approach for realizing high-frequency Gm-C continuous-time filters is proposed and a circuit implementation is presented. The design approach is based on reducing the effects of the finite impedance at each output node by placing a controlled output active load whose value is taken into account in the filter design. The implementation uses a BiCMOS high-efficiency fully-differential transconductor with an all-passive common-mode feedback. Simulation results of a biquadratic low-pass filter with cut-off frequency up to 82 MHz and load capacitance as large as 3pF conclude the paper
    Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on; 07/1994
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    ABSTRACT: A novel linearization circuit for a tunable BiCMOS transconductor based on the emitter degeneration of bipolar devices is analyzed. The transconductor is suitable for high-frequency continuous-time filter implementations because of the large value of the gm/I ratio and its ease of tunability. An integrator cell with a unity gain bandwidth of up to 80 MHz can be realized with a capacitive load as large as 3 pF and a power consumption of about 3.5 mW. An extended tuning range can be achieved through the proposed linearization circuit that reduces the total harmonic distortion (THD) in the lower part of the tuning range. Simulation program with IC emphasis (SPICE) simulation results are presented, comparing the classical solution with respect to the linearized one; the input stage shows an output current THD less than 1% for an input differential signal of up to 500m V<sub>pp</sub> over an almost 10:1 tuning range
    Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on; 06/1993
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    ABSTRACT: A high-speed fully-differential operational amplifier (op-amp) realized in 2-μ BiCMOS technology is proposed. Input MOS buffers allow the use of this op-amp in switched capacitor (SC) circuits with high clock frequency (up to 75 MHz). The gain stage is realized with resistively-loaded bipolar devices. No common mode feedback is required. This saves area and power and increases speed. The op-amp presents a DC gain of about 46 dB with a unity-gain frequency as large as 700 MHz with 1.5 pF load. The measured performance of closed-loop settling time (1%) is about 12 ns
    Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on; 01/1993
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    ABSTRACT: A BiCMOS fully differential transconductor based on MOS transistors operating in the linear region is presented. The circuit has an equivalent nondominant pole located above 1.5 GHz. This makes it suitable for high-frequency continuous-time filters. A second-order low-pass filter using the new transconductor realized in a 2-μm BiCMOS technology is reported. The cutoff frequency f <sub>0 </sub> of the cell is tunable in the range of 8-32 MHz and the quality factor is 2. The filter THD stays lower than -40 dB for an output signal up to 3.2 V<sub>p-p</sub> at 5-MHz frequency. The area of the cell is 0.322 mm<sup>2</sup> and the power consumption (with f <sub>0 </sub>=25 MHz) is 30 mW with a single 5-V power supply
    IEEE Journal of Solid-State Circuits 01/1993; · 3.06 Impact Factor
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    ABSTRACT: A circuit for the detection of the threshold voltage V <sub>TH</sub> of MOS devices is presented. The basic scheme proposed here is implemented in BiCMOS technology but can also be applied in any standard CMOS process. The deviation of the detected V <sub>TH </sub> from the actual (or extrapolated) one is analytically estimated, taking into account the effects due to channel length modulation and mobility modulation. The results obtained show that the error at ambient temperature is lower than 0.6% for all values of V <sub>DD</sub> larger than 3.25 V, and for temperatures in the range -25°C to 125°C the error is never higher than 4%
    Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on; 06/1992
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    ABSTRACT: A new transconductor stage in BiCMOS technology is presented. The main characteristics of the stage are: high linearity of operation, non-dominant poles in the range of gigahertzs, low noise and operation from a single 5V power supply. A 2nd-order lowpass filter cell based on this transconductor has been designed and realized in a 2¿m BiCMOS technology. The cutoff frequency fo of the cell can be tuned in the range of 8-32MHz; the quality factor is 2. The filter THD stays lower than 40dB for an output signal up to 3.2Vpp at 5MHz frequency. The area of the cell is 500 mils<sup>2</sup> and the power consumption (with f o = 25MHz) is 30mW.
    Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European; 10/1991
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    ABSTRACT: A novel approach in the design of high-frequency switched capacitor (SC) circuits is presented. It is based on the use of simple and fast amplifiers with low but precisely controlled gain value. The effect of the precisely known and stable opamp gain is compensated for by changing the capacitor values during the synthesis of the SC cell. An example of an opamp with these features and the synthesis of a biquadratic filter based on this approach are given.
    Electronics Letters 08/1991; · 1.04 Impact Factor
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    ABSTRACT: A differential transconductance stage implemented in BiCMOS technology is described. The key features of the new stage are: (1) a total harmonic distortion (THD) less than 0.15% up to a 3 V<sub>pp</sub> differential input signal, assuming 2% mismatch of the input devices, with a 5-V supply; (2) a second pole frequency typically higher than 2 GHz; and (3) a gain of more than 50 dB. All of these features are obtained from simulations performed using SPICE and correspond to a BiCMOS process featuring 2-μm minimum channel length and 7-GHz bipolar f <sub>T</sub>. The structure of the transconductance is described and its operation explained. The nonidealities of the stage, like distortion, finite gain, parasitic poles, noise, and offset, are discussed. The complete implementation is presented. The simulated performance of a bandpass filter based on the new transconductor is reported. The results demonstrate that using the new circuit a filter centered around 5 MHz with a Q of 22 should result in a Q precision better than 12% without any Q tuning
    Circuits and Systems, 1990., IEEE International Symposium on; 06/1990