Publications (4)11.37 Total impact
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Article: Wafer-scale high-throughput ordered arrays of Si and coaxial Si/Si(1-x)Ge(x) wires: fabrication, characterization, and photovoltaic application.
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ABSTRACT: We have developed a method combining lithography and catalytic etching to fabricate large-area (uniform coverage over an entire 5-in. wafer) arrays of vertically aligned single-crystal Si nanowires with high throughput. Coaxial n-Si/p-SiGe wire arrays are also fabricated by further coating single-crystal epitaxial SiGe layers on the Si wires using ultrahigh vacuum chemical vapor deposition (UHVCVD). This method allows precise control over the diameter, length, density, spacing, orientation, shape, pattern and location of the Si and Si/SiGe nanowire arrays, making it possible to fabricate an array of devices based on rationally designed nanowire arrays. A proposed fabrication mechanism of the etching process is presented. Inspired by the excellent antireflection properties of the Si/SiGe wire arrays, we built solar cells based on the arrays of these wires containing radial junctions, an example of which exhibits an open circuit voltage (V(oc)) of 650 mV, a short-circuit current density (J(sc)) of 8.38 mA/cm(2), a fill factor of 0.60, and an energy conversion efficiency (η) of 3.26%. Such a p-n radial structure will have a great potential application for cost-efficient photovoltaic (PV) solar energy conversion.ACS Nano 08/2011; 5(8):6629-36. · 10.77 Impact Factor -
Article: Wafer-Scale High-Throughput Ordered Arrays of Si and Coaxial Si/Si1–xGex Wires: Fabrication, Characterization, and Photovoltaic Application
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ABSTRACT: We have developed a method combining lithography and catalytic etching to fabricate large-area (uniform coverage over an entire 5-in. wafer) arrays of vertically aligned single-crystal Si nanowires with high throughput. Coaxial n-Si/p-SiGe wire arrays are also fabricated by further coating single-crystal epitaxial SiGe layers on the Si wires using ultrahigh vacuum chemical vapor deposition (UHVCVD). This method allows precise control over the diameter, length, density, spacing, orientation, shape, pattern and location of the Si and Si/SiGe nanowire arrays, making it possible to fabricate an array of devices based on rationally designed nanowire arrays. A proposed fabrication mechanism of the etching process is presented. Inspired by the excellent antireflection properties of the Si/SiGe wire arrays, we built solar cells based on the arrays of these wires containing radial junctions, an example of which exhibits an open circuit voltage (Voc) of 650 mV, a short-circuit current density (Jsc) of 8.38 mA/cm2, a fill factor of 0.60, and an energy conversion efficiency (η) of 3.26%. Such a p–n radial structure will have a great potential application for cost-efficient photovoltaic (PV) solar energy conversion.Keywords: Si wires arrays; radial Si/Si1−xGex wire arrays; single crystal epitaxial growth; PV application07/2011; -
Article: A new method of fabricating strained Silicon materials
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ABSTRACT: Strain-relaxed SiGe virtual substrates are of great importance for fabricating strained Si materials. Instead of using graded buffer method to obtain fully relaxed SiGe film, in this study a new method to obtain relaxed SiGe film and strained Si film with much thinner SiGe film was proposed. Almost fully relaxed thin SiGe buffer layer was obtained by Si/SiGe/Si multi-structure oxidation and the SiO2 layer removing before SiGe regrowth. Raman spectroscopy analysis indicates that the regrown SiGe film has a strain relaxation ratio of about 93% while the Si cap layer has a strain of 0.63%. AFM shows good surface roughness. This new method is proved to be a useful approach to fabricate thin relaxed epilayers and strain Si films.Rare Metals 25(6):41-44. · 0.59 Impact Factor -
Article: A universal electron mobility model of strained Si MOSFETs based on variational wave functions
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ABSTRACT: A new model is proposed to describe the electron mobility enhancement in strained Si MOSFETs inversion layers using the variational wave functions in the triangular potential approximation. Phonon scattering and surface roughness scattering are included in this model and electron mobility enhancements due to the suppression of these two scatterings are accounted for, respectively. A process-dependent interface parameter is introduced to fit with various technologies. Results from the model show good agreement with experiments for different Ge mole fractions and for a wide range of vertical effective field and temperature. The model is very interesting for implementation in conventional device simulators.Solid-State Electronics.
