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ABSTRACT: The integration of low- and ultralow-k SiCOH dielectrics in the interconnect structures of very large scale integrated chips involves complex stacks with multiple interfaces. Successful fabrication of reliable chips requires strong adhesion between the different layers of the stacks. A critical interface in the dielectric stack is the interface between the SiCNH diffusion cap and the SiCOH inter- and intralevel dielectrics (ILDs). It was observed that, due to the original deposition conditions, the interface layer was weakened both by a low adhesion strength between SiCNH and SiCOH and by the formation of an initial layer of SiCOH with reduced cohesive strength. The manufacturing process has been modified to engineer this interface and obtain interfacial strengths close to the cohesive strengths of the bulk ILDs. This paper discusses the causes for the original low interfacial strength and presents an approach for enhancing it by engineering the interface to the cap for both the dense SiCOH and porous SiCOH ILDs.
Journal of Applied Physics 03/2008; 103(5):054104-054104-6. · 2.17 Impact Factor
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M. Farooq,
I. Melville,
C. Muzzy,
P.V. McLaughlin,
R. Hannon,
W. Sauter,
J. Muncy,
D. Questad,
C. Carey,
M. Cullinan-Scholl,
V. McGahay,
M. Angyal,
H. Nye, M. Lane,
Xiao Hu Liu,
T. Shaw,
C. Murray
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ABSTRACT: This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.
International Interconnect Technology Conference, IEEE 2007; 07/2007
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V. McGahay,
G. Bonilla,
F. Chen,
C. Christiansen,
S. Cohen,
M. Cullinan-Scholl,
J. Demarest,
D. Dunn,
B. Engel,
J. Fitzsimmons, [......],
H. Shobha,
E. Simonyi,
J. Widodo,
A. Grill,
R. Hannon, M. Lane,
H. Nye,
T. Spooner,
R. Wisnieff,
T. Ivers
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ABSTRACT: A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and process-induced damage were successfully overcome. Yield and interconnect reliability metrics comparable to dense K=3 SiCOH have been achieved. Package deep thermal cycle showed sensitivity to assembly which is controllable though chip edge structural engineering
Interconnect Technology Conference, 2006 International; 07/2006
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C.-C. Yang,
T. Spooner,
S. Ponoth,
K. Chanda,
A. Simon,
C. Lavoie, M. Lane,
C.-K. Hu,
E. Liniger,
L. Gignac,
T. Shaw,
S. Cohen,
F. McFeely,
D. Edelstein
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ABSTRACT: Thin film characterization, electrical performance, and preliminary reliability of physical vapor-deposited (PVD) TaN/chemical vapor-deposited (CVD) Ru bilayer were carried out to evaluate its feasibility as a liner layer for back-end of line (BEOL) Cu-low k integration. Adhesion and barrier strength were studied using 4-point bend, X-ray diffraction (XRD), and triangular voltage sweep (TVS) techniques. Electrical yields and line/via resistances were measured at both single and dual damascene levels, with PVD TaN/Ta liner layer as a baseline control. Reliability studies included electromigration (EM) and current-voltage (I-V) breakdown tests
Interconnect Technology Conference, 2006 International; 07/2006
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S. Nitta,
S. Purushothaman,
S. Smith,
M. Krishnan,
D. Canaperi,
T. Dalton,
W. Volksen,
R.D. Miller,
B. Herbst,
C.K. Hu,
E. Liniger,
J. Lloyd, M. Lane,
D.L. Rath,
M. Colburn,
L. Gignac
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ABSTRACT: In this communication, a novel scheme known as the etch back/gapfill (EBGF) integration scheme was introduced and shown to overcome most of the well known challenges (2) that are expected to complicate the integration of porous low k materials. It was shown that this integration scheme can be used to successfully generate multi-level dual damascene structures using intermetal dielectric (IMD) materials with k less than 2.0 with promising yield and reliability. It has been demonstrated that EBGF integration is a promising method to integrate fragile porous low k materials into BEOL structures by avoiding most of the major processing issues associated with such materials. By using this scheme, new ultra-low k and extreme low k materials can be introduced with limited modification to the existing dense IMD fabrication infrastructure while increasing the performance of the interconnects substantially. As such the method offers a potential to break through what is now commonly referred to as the "red brick wall" in the BEOL part of the ITRS roadmap.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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W. Landers,
D. Edelstein,
L. Clevenger,
C. Das,
C.-C. Yang,
T. Aoki,
F. Beaulieu,
J. Casey,
A. Cowley,
M. Cullinan, [......], M. Lane,
X. Liu,
T. Lombardi,
C. McCarthy,
C. Muzzy,
J. Nadeau-Filteau,
D. Questad,
W. Sauter,
T. Shaw,
J. Wright
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ABSTRACT: A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K ∼ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM's internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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D. Edelstein,
C. Davis,
L. Clevenger,
M. Yoon,
A. Cowley,
T. Nogami,
H. Rathore,
B. Agarwala,
S. Arai,
A. Carbone, [......],
A. Simon,
E. Simonyi,
S. Tempest,
T. Van Kleeck,
S. Vogt,
Y.-Y. Wang,
W. Wille,
J. Wright,
C.-C. Yang,
T. Ivers
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ABSTRACT: We report a comprehensive characterization of a 90 nm CMOS technology with Cu/SiCOH low-k interconnect BEOL. Significant material and integration engineering have led to the highest reliability, without degrading the performance expected from low-k. Results are presented on every aspect of BEOL and chip-package reliability, yields, low-k film parameters, BEOL capacitances and circuit delays on functional chips. All results meet or exceed our concurrent 90 nm Cu/FTEOS technology, and support extendibility to 65 nm.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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A. Grill,
D. Edelstein,
D. Restaino, M. Lane,
S. Gates,
E. Liniger,
T. Shaw,
X.H. Liu,
D. Klaus,
V. Patel, [......],
E. Simonyi,
N. Klymko,
S. Lane,
K. Ida,
S. Vogt,
T. Van Kleeck,
C. Davis,
M. Ono,
T. Nogami,
T. Ivers
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ABSTRACT: The research integration of SiCOH films in a reliable ULSI integrated circuit chip imposes many requirements on the properties of the dielectric material. This paper describes a selection and optimization process for choosing the best film to be integrated in Cu wiring levels of ULSI CMOS chips in the 90 nm technology node.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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R.G. Filippi,
J.F. McGrath,
T.M. Shaw,
C.E. Murray,
H.S. Rathore,
P.S. McLaughlin,
V. McGahay,
L. Nicholson,
P.-C. Wang,
J.R. Lloyd, [......],
G. Goth,
E. Barth,
G. Biery,
C.R. Davis,
R.A. Wachnik,
R. Goldblatt,
T. Ivers,
A. Swinton,
C. Barile,
J. Aitken
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ABSTRACT: The reliability of a stacked via chain stressed under various thermal cycle conditions is described. The chain consists of Cu Dual Damascene metallization with SiLK (trademark of Dow Chemical) as the organic low-k dielectric. Failure analysis indicates that cracks form in the Cu vias during thermal cycle stress. Due to the presence of two failure modes, the thermal cycle statistical behavior is described by a bimodal lognormal failure distribution. The thermal cycle lifetime exhibits a strong dependence on the temperature range and a rather weak dependence, on the maximum temperature in the cycle. Evidence of a threshold temperature range below which thermal cycle fails should not occur as well as a correlation between the test structure yield and reliability are also reported.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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D. Edelstein,
H. Rathore,
C. Davis,
L. Clevenger,
A. Cowley,
T. Nogami,
B. Agarwala,
S. Arai,
A. Carbone,
K. Chanda, [......],
E. Simonyi,
A. Swift,
T. Van Kleeck,
S. Vogt,
Y.-Y. Wang,
W. Wille,
J. Wright,
C.-C. Yang,
M. Yoon,
T. Ivers
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ABSTRACT: Integration and development of Cu Back-End of Line (BEOL) with PECVD low-k organosilicate glass (OSG, also called SiCOH, carbon-doped oxide, CDO, etc.) for 130 nm and 90 nm CMOS technologies has been reported by a number of institutions. Here we report on a Cu/SiCOH technology which has similarities, but also enhanced integration and reliability characteristics while preserving the R and C performance levels. These enhancements have led to excellent reliability results reported here, and are expected to increase the robustness to high-volume manufacturing and extendibility to next-generation smaller dimensions. The SiCOH and cap mechanical, chemical, and electrical strengths are increased, as well as associated interfacial adhesions. These combine with an optimized Cu metallization. As chip-package reliability is most at risk for low-k dielectrics, improvements have been brought into the BEOL level structure, the kerf design, and in some cases new packaging materials. When combined with the dielectric material and interface improvements, redundancy exists in the protection against potential chip-packaging failures. No failures occur in the full rounds of chip-package reliability stress testing done here on multiple wirebond and flip-chip packages. These packaging and other reliability results are presented, including BEOL-specific tests [electromigration (E-M), stress-migration (S-M), time-dependent dielectric breakdown (TDDB), thermal cycling (T/C)], environmental [temperature-humidity-bias (THB)], and functional stressing of product modules. The stress criteria and results exceeded JEDEC standards. All Cu/SiCOH tests passed at the same levels as our concurrent 90 nm Cu/SiOF technology.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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ABSTRACT: Grass hedges are narrow (1–2 m wide) parallel strips of stiff, erect, grass planted near to or on the contour of fields but crossing swale areas at angles convenient for farming. They serve as guides for contour cultivation, retard and disperse surface runoff, cause deposition of eroded sediment, and reduce ephemeral gully development. After three years of tilled fallow between mixed-species hedges, the average grade of 18 m wide tilled strips between 1.5 m wide hedges was reduced from 0.068 to 0.052 as a result of surface lowering below hedges and on the shoulders of swale areas combined with increases in elevation above hedges. Annual surveys show progressive lowering of high spots and filling of low spots as contours lines more closely aligned with hedges. Survey data indicated annual erosion rates of nearly 250 t ha−1 year−1. Both RUSLE and WEPP over-predicted erosion rates, partly because backwater and slope modification affects were not considered. A tillage translocation model predicted enough soil movement to account for 30–60% of the observed changes. A combination of tillage translocation and water erosion/deposition provides the best explanation for the observed aggradation/degradation patterns.
Soil and Tillage Research.
