A. Fujimaki

Nagoya University, Nagoya, Aichi, Japan

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Publications (220)260.03 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: We present not the results but the idea of a superconducting nanowire detector with ^{10} B conversion layer for sensing a single neutron. We use 7 Li ion and 4 He ion emitted as two independent heat sources, which appear in opposite direction associated with nuclear reaction ^{10} B(n,4 He)7 Li. We probe a change in the kinetic inductance L_k coming from inertia of the Cooper pairs. Our detector is different from a conventional kinetic inductance detector (KID), but is named as a current-biased KID. We use two sets of Nb nanowires with superconducting readout taps to monitor the local signal. In between the X meander and the Y meander, we inserted a ^{10} B layer acting as a conversion layer from neutrons to charged particles. We plan to fabricate a mega-pixel neutron imager by coupling 10 bit linear position-sensitive arrays along the X and Y directions with the single flux quantum readout circuits.
    Journal of Low Temperature Physics 03/2014; 176(3-4). · 1.18 Impact Factor
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    ABSTRACT: We recently proposed the idea of a novel sort of superconducting detector, i.e., a current-biased kinetic inductance detector (CB-KID). This detector is different from a current-biased transition edge detector studied previously, and is able to sense a change in kinetic inductance L_k given by Lk = Λ kl/S = msl/ns{qs}2S (Λ k ; kinetic inductivity, m_s ; mass of Cooper pair, n_s ; density of Cooper pairs, q_s ; charge of Cooper pair, l ; length of device, S ; cross sectional area) under a constant dc bias current I_b . In the present work, we first extend this idea to construct a multi-channel CB-KIDs array made of 200-nm-thick MgB_2 thin-film meanderline with 3-\upmu m thin wire. We succeeded in observing clear signals for imaging from the four-channel CB-KIDs at 4 K by irradiating focused pulsed laser. A scanning laser spot can be achieved by an XYZ piezo-driven stage and an optical fiber with an aspheric focused lens. We can see typical signals from all 4 channels at 4 K, and obtain the positional dependence of the signal as the contour in XY plane. Our CB-KIDs can be used as neutron detectors by utilizing energy released from a nuclear reaction between ^{10} B and cold neutron.
    01/2014;
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    ABSTRACT: We evaluated the current sensitivity of a quasi-one-junction SQUID (QOS) comparator with an input transformer at 4.2 K. A comparator based on a QOS is promising for constructing the single flux quantum (SFQ) readout circuits of an array system of multiple superconducting detectors.The QOS comparator is made of three Nb/AlO_x /Nb Josephson junctions, senses an output signal of a superconductor detector, and generates the SFQ pulses.There are strong demands for enhancing the current sensitivity of the QOS comparator because an output current from superconducting detector typically remains at the magnitude of a few \upmu A. We fabricated the QOS comparator with an input transformer using AIST Standard Process 2, where the critical current density of the Josephson junctions is chosen as high as 2.5 kA/cm2 . We designed the input transformer to enhance the current sensitivity under the conditions of 200 \upmu m × 200 \upmu m in size and 20:1 in turn ratio. Consequently, we succeeded in reducing a gray zone width of the comparator, and achieved the current sensitivity of 400 nA at 4.2 K in the low frequency range.
    Journal of Low Temperature Physics 01/2014; 176(3-4). · 1.18 Impact Factor
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    ABSTRACT: This paper describes the design and testing of an 8-bit asynchronous wave-pipelined sparse-tree RSFQ Arithmetic Logic Unit (ALU). Compared to previously developed RSFQ ALUs, this unit features an extensive set of 8 arithmetic and 12 logical operations. The execution of ALU operations consists of two steps. First, when necessary, one or both operands are inverted, and then operations are performed on these preprocessed data. Unlike the RSFQ Kogge-Stone-based designs, our parallel-prefix sparse-tree ALU has significantly reduced circuit complexity while maintaining robust operational margins at high frequency. An 8-bit ALU has been implemented with the ISTEC 10 kA/cm^2 1.0 μm 9-metal ADP2.1 fabrication process as a joint effort between Stony Brook University, Yokohama National University, and Nagoya University. Using the CONNECT cell library and SFQ CAD tools developed at Nagoya and Yokohama, the Stony Brook team has developed the complete logical and physical design of the ALU chip. The 8-bit ALU core (without SFQ-to-DC and DC-to-SFQ converters) consists of 8832 Josephson junctions with an area of 7.2 mm^2. Simulations show that the ALU can operate at the maximum rate of 42 GHz. It has the latency of 374 ps at a bias voltage of 2.5 mV. The chip was fabricated and tested at low frequency in 2012. Testing results showed malfunctioning of some gates but despite these shortcomings we still verified several ALU operations with the measured DC bias voltage margins of ±1.8%.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3). · 1.20 Impact Factor
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    ABSTRACT: In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor RSFQ adder implemented using ISTEC 10 kA/cm^2 ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-DC and DC-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm^2. It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8% / -10.7%. Another adder chip consisting of 12785 junctions with additional on-chip circuits for 30 GHz testing was also fabricated but its testing showed the need for another fabrication run.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3). · 1.20 Impact Factor
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    ABSTRACT: We will discuss the microarchitecture, design, and testing of the first 8x8-bit (by modulo 256) parallel carry-save superconductor RSFQ multiplier implemented using the ISTEC 10 kA/cm^2 1.0 μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8x8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80 GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly-regular layout with both local and global connections between modules. The multiplier core (without SFQ-to- DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm^2. The multiplier is designed with the target operation frequency of 20 GHz, and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3). · 1.20 Impact Factor
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    ABSTRACT: We evaluated the relationship between the gray zone width and the operating margin for comparators composed of quasi-one-junction superconducting quantum interference devices (QOSs) with shunt resistors, which are often used as high-speed readout circuits in multiple superconductor detector systems. The gray zone width is a good measure of current sensitivity of a single-bit comparator. We numerically analyzed the gray zone width of a QOS comparator and determined the circuit parameters. The gray zone width obtained from the experiments concurred with the results of the numerical analysis and was 2--3 μA at 4.2 K in a QOS comparator composed of three Nb/AlOx/Nb junctions with critical currents of less than 90 μA. The experimentally obtained operating margin for the bias current provided to the comparator was ± 15% at the bias current of around 140 μA. These results show that QOS comparators are promising for readout circuits operating up to tens of GHz and imply that gray zone width is the thermal noise in the resistors at 4.2 K.
    Japanese Journal of Applied Physics 03/2013; 52(3):3101-. · 1.07 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We will discuss the microarchitecture, design, and testing of the first 8 × 8-bit (by modulo 256) parallel carry-save RSFQ multiplier implemented using the ISTEC 10- kA/cm2 1.0-μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8 × 8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly regular layout with both local and global connections between modules. The multiplier core (without SFQ-to-DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm2 . The multiplier is designed with the target operation frequency of 20 GHz and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.
    IEEE Transactions on Applied Superconductivity 01/2013; 23(3):1300104-1300104. · 1.20 Impact Factor
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    ABSTRACT: We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In our previous study, we implemented an SFQ half-precision (16-bit) bit-serial FPA using the ISTEC 2.5 kA/cm2 standard process, and demonstrated the correct operations at 24 GHz by on-chip high-speed tests. In this study, we designed and implemented an SFQ half-precision bit-serial FPA using a cell library for the AIST 10 kA/cm2 Nb nine-metal-layer process (ADP2), and carried out on-chip high speed tests. The designed FPA contains 9661 Josephson junctions and occupies a circuit area of 12.95 mm2. Its target operation frequency is 50 GHz. We have demonstrated the correct operation of the FPA at the maximum frequency of 62 GHz although there is a functional error in the design. The measured DC bias margin ranges from 102% to 108% at 50 GHz operation. The total power consumption is measured to be 2.9 mW.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
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    ABSTRACT: We present a new design technique of rapid single-flux-quantum (RSFQ) logic gates for low-noise, high-speed operation. In this study, we propose the use of a damping resistor shared with a junction pair composing a comparator, in addition to their individual shunt resistors increased from the standard values. We analyzed timing characteristics and bit error rates (BERs) of several RSFQ flip-flops composed of the proposed comparators using numerical simulation. The proposed comparator showed reduced timing jitter by ~5% in association with small delay time, sharpened BER curves, and improvement in operating margins by 2-3% compared to the standard design. We fabricated 2-bit shift registers using the noise reduction technique. We obtained sharp BER curves from the measurement. The proposed method indicated that it gave wide margins.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
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    ABSTRACT: We report successful operations of low-energy consumption rapid single-flux-quantum (RSFQ) circuits applying lowered driving voltages, called LV-RSFQ, using different fabrication processes. In the LV-RSFQ, we feed bias currents to Josephson junctions from lowered constant voltages (less than 1 mV) through small resistors without extra inductors. Both static and dynamic energy consumption are reduced because of suppression of amplitudes of SFQ pulses, in exchange for slower switching speed. We show that the switching speed in LV-RSFQ circuits is improved by increasing critical current density of Josephson junctions. We demonstrated high-speed operations of LV-RSFQ shift registers in a range of 5-40 GHz and 15-90 GHz using the 2.5-kA/cm2 and 10-kA/cm2 fabrication technologies, respectively. Comparison of the experimental results of the LV-RSFQ circuits fabricated using two different technologies derives the optimum bias voltage in terms of energy-delay product ranged from 0.1 to 1.0 ICRS, where ICRS is the product of Josephson critical current and shunt resistance.
    IEEE Transactions on Applied Superconductivity 01/2013; 23(3):1701104-1701104. · 1.20 Impact Factor
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    ABSTRACT: We studied high-frequency characteristics of dc-SQUIDs with magnetic-nanoparticle-film patterns, which would be applied to superconductor integrated circuits for reducing widths in passive transmission lines and for increasing coupling factors in transformers. The patterns were constructed by Fe3O4 nanoparticles (NPs) with an average diameter of 5 nm. The high-frequency characteristics were obtained by comparison in the resonant characteristics and threshold characteristics of the SQUIDs before and after formation of the patterns. The n-th resonant frequency (fn) was calculated from the n-th resonant voltage step of the SQUID, giving the LC product at fn. Here, L is the SQUID loop inductance, and C is the equivalent capacitance consisting of Josephson junction of the SQUID and the NP pattern. In SQUIDs with large NP patterns, the LC product increased from 8% to 260% at frequencies of 47 GHz or higher with the thickness of the pattern although the increase in inductance of the SQUID in threshold characteristics was from 0.9% to 5.5%. On the other hand, the increase in LC product caused by a small pattern was negligible regardless of a 7.6% increase in inductance in threshold characteristics.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
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    ABSTRACT: We report experimental results of bit-error-rate (BER) measurements in small-critical-current or lowered-biasvoltage rapid single-flux-quantum (RSFQ) circuits for power reduction. In such reduced-power RSFQ circuits, the BERs can be increased because of the reduced signal-to-noise ratio. We fabricated 2-bit shift registers using a 2.5-kA/cm2 niobium process, and measured BERs by low-frequency tests at 4.2 K. We obtained sufficiently wide bias margins when we reduced the critical currents in a range of 1/2 to 1/4 of the conventional design, while it narrowed as the critical currents reduced to 1/8. For low-voltage shift registers, the bias margins linearly decreased in width as bias voltages were lowered. We found that 0.25 mV, 1/10 of the conventional design, was a good bias voltage to balance competing power reduction and bias margin.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
  • H. Akaike, T. Funai, S. Sakamoto, A. Fujimaki
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    ABSTRACT: We have evaluated the electrical characteristics of NbN/Al-AlNx/NbN tunnel junctions fabricated on sapphire-C or fused-silica substrates. NbN/Al-AlNx/NbN multilayers were prepared by reactive dc-magnetron sputtering deposition of lower and upper NbN layers, and rf-magnetron sputtering deposition of the Al layer, followed by radical-nitridation. The junctions showed low sub-gap leakage currents in the current-voltage characteristics at 4.2 K. The quality parameter, Rsg/Rn, where respective Rsg and Rn are the sub-gap resistance at 2 mV and junction resistance at 5 mV, was above 15. The gap voltage (Vg) was around 3.3 mV, which was reduced in comparison with Vg values of ~4.3 mV for junctions on MgO substrates. The reduced Vg was caused by superconducting properties of lower NbN layers deposited on the sapphire or fused-silica substrates. Uniformity in critical current (Ic) was relatively good, and the maximum-to-minimum spread in Ic was ±1.7% for 200 junctions on a sapphire substrate and ±2.0% for the junctions on a fused-silica substrate.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
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    ABSTRACT: The decision of a Josephson comparator is influenced by thermal noise which is limiting the practical sensitivity in many applications of superconductor electronics. We analyzed the Gaussian state distribution theoretically and identified the most effective way to improve the practical sensitivity of a Josephson comparator. We suggest a modified damping concept and demonstrate a gray zone width as low as 840 nA experimentally. This value is about ten times smaller than for conventional Josephson comparators and very close to the theoretical limit at liquid helium temperature.
    Journal of Applied Physics 06/2012; 111(12). · 2.21 Impact Factor
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    ABSTRACT: We have successfully obtained asymmetrical current--voltage (I--V) characteristics in YBa2Cu3O7-x (YBCO) nanobridges patterned with asymmetrical geometry. These asymmetrical nanobridges (ANBs) are shown to control vortices one at a time. The critical current Ic, of 200-nm-wide and 100-nm-thick ANB changes by a maximum of 9% when a magnetic field of 2.4 mT is applied. The Ic variation Δ Ic increases monotonically with increased magnetic field from -2.2 to 2.4 mT. The asymmetrical I--V characteristics obtained in our experiment are due to the restriction of vortex motion by the asymmetrical surface barrier (the so-called vortex ratchet effect). The width and thickness dependencies of the I--V asymmetry are also studied, and indicate that the bias current and the Meissner screening current, determined by the relative width compared to the effective penetration depth of the YBCO film, dominates the I--V asymmetry characteristics.
    Japanese Journal of Applied Physics 05/2012; 51(5):3101-. · 1.07 Impact Factor
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    ABSTRACT: We demonstrate rapid single-flux-quantum (RSFQ) circuits with reduced energy consumption by lowering the driving voltages and critical currents of Josephson junctions (JJs). At lowered voltages, the energy statically consumed by bias resistors (which is dominant in RSFQ circuits) is reduced. In addition, we show that when RSFQ circuits are driven by lowered constant voltages, the dynamic energy consumption resulting from the switching of JJs is reduced because of the suppression of the amplitudes of the signal voltage pulses, even though the switching speed becomes slower. Utilization of miniaturized JJs with smaller critical currents also leads to the reduction of static and dynamic energy consumption without decreasing the switching speed. We have designed and tested ultra-low-energy 8-bit shift registers, and verified the correctness of high-speed operations up to 18 GHz. The average energy consumption, including that at the bias resistors, was measured at 4.0 aJ/bit, which represents an energy efficiency two orders of magnitude better than that of standard RSFQ circuits.
    Japanese Journal of Applied Physics 05/2012; 51(5):3102-. · 1.07 Impact Factor
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    ABSTRACT: We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 kA/cm<sup>2</sup> and advanced 10 kA/cm<sup>2</sup> processes and successfully tested at high speed.
    IEEE Transactions on Applied Superconductivity 07/2011; · 1.20 Impact Factor
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    ABSTRACT: We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm<sup>2</sup> Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.
    IEEE Transactions on Applied Superconductivity 07/2011; · 1.20 Impact Factor
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    ABSTRACT: This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm<sup>2</sup> and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.
    IEEE Transactions on Applied Superconductivity 07/2011; · 1.20 Impact Factor

Publication Stats

849 Citations
260.03 Total Impact Points

Institutions

  • 1991–2014
    • Nagoya University
      • Department of Quantum Engineering
      Nagoya, Aichi, Japan
  • 2003–2009
    • Yokohama National University
      • Department of Physics, Electrical and Computer Engineering
      Yokohama-shi, Kanagawa-ken, Japan
  • 2005
    • International Superconductivity Technology Center
      Sakado, Saitama, Japan
  • 1999–2003
    • Kinki University
      • Faculty of Biology-Oriented Science and Technology
      Ōsaka-shi, Osaka-fu, Japan
  • 2001
    • Osaka University
      • The Institute of Scientific and Industrial Research (ISIR)
      Ibaraki, Osaka-fu, Japan
  • 1995
    • Toyota National College of Technology
      Koromo, Aichi, Japan