Akira Fujimaki

Nagoya University, Nagoya, Aichi, Japan

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Publications (228)299.06 Total impact

  • IEEE Transactions on Applied Superconductivity 06/2015; 25(3):1-4. DOI:10.1109/TASC.2014.2385480 · 1.32 Impact Factor
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    ABSTRACT: We present not the results but the idea of a superconducting nanowire detector with ^{10} B conversion layer for sensing a single neutron. We use 7 Li ion and 4 He ion emitted as two independent heat sources, which appear in opposite direction associated with nuclear reaction ^{10} B(n,4 He)7 Li. We probe a change in the kinetic inductance L_k coming from inertia of the Cooper pairs. Our detector is different from a conventional kinetic inductance detector (KID), but is named as a current-biased KID. We use two sets of Nb nanowires with superconducting readout taps to monitor the local signal. In between the X meander and the Y meander, we inserted a ^{10} B layer acting as a conversion layer from neutrons to charged particles. We plan to fabricate a mega-pixel neutron imager by coupling 10 bit linear position-sensitive arrays along the X and Y directions with the single flux quantum readout circuits.
    Journal of Low Temperature Physics 03/2014; 176(3-4). DOI:10.1007/s10909-014-1159-8 · 1.04 Impact Factor
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    ABSTRACT: We evaluated the effects of Fe3O4 magnetic nanoparticle (NP) films on the electrical characteristics of superconducting quantum interference devices (SQUIDs) at 4.2 K to enhance the performance of superconducting circuits. The NP films were formed directly on the SQUIDs. For SQUIDs with 5-nm-NP films, the SQUID inductance increased almost linearly with the NP film thickness, reaching 19.7% at an NP film thickness of 990 nm. An increase in NP size from 5 to 20 nm reduced that in the SQUID inductance. On the other hand, no clear effects on the current–voltage characteristics of SQUIDs were observed for 5- and 10-nm-NP films, while the critical currents of some SQUIDs with 20-nm-NP films were reduced.
    Japanese Journal of Applied Physics 03/2014; 53(3):033101. DOI:10.7567/JJAP.53.033101 · 1.06 Impact Factor
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    ABSTRACT: We evaluated the current sensitivity of a quasi-one-junction SQUID (QOS) comparator with an input transformer at 4.2 K. A comparator based on a QOS is promising for constructing the single flux quantum (SFQ) readout circuits of an array system of multiple superconducting detectors.The QOS comparator is made of three Nb/AlO_x /Nb Josephson junctions, senses an output signal of a superconductor detector, and generates the SFQ pulses.There are strong demands for enhancing the current sensitivity of the QOS comparator because an output current from superconducting detector typically remains at the magnitude of a few \upmu A. We fabricated the QOS comparator with an input transformer using AIST Standard Process 2, where the critical current density of the Josephson junctions is chosen as high as 2.5 kA/cm2 . We designed the input transformer to enhance the current sensitivity under the conditions of 200 \upmu m × 200 \upmu m in size and 20:1 in turn ratio. Consequently, we succeeded in reducing a gray zone width of the comparator, and achieved the current sensitivity of 400 nA at 4.2 K in the low frequency range.
    Journal of Low Temperature Physics 01/2014; 176(3-4). DOI:10.1007/s10909-014-1119-3 · 1.04 Impact Factor
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    ABSTRACT: We recently proposed the idea of a novel sort of superconducting detector, i.e., a current-biased kinetic inductance detector (CB-KID). This detector is different from a current-biased transition edge detector studied previously, and is able to sense a change in kinetic inductance L_k given by Lk = Λ kl/S = msl/ns{qs}2S (Λ k ; kinetic inductivity, m_s ; mass of Cooper pair, n_s ; density of Cooper pairs, q_s ; charge of Cooper pair, l ; length of device, S ; cross sectional area) under a constant dc bias current I_b . In the present work, we first extend this idea to construct a multi-channel CB-KIDs array made of 200-nm-thick MgB_2 thin-film meanderline with 3-\upmu m thin wire. We succeeded in observing clear signals for imaging from the four-channel CB-KIDs at 4 K by irradiating focused pulsed laser. A scanning laser spot can be achieved by an XYZ piezo-driven stage and an optical fiber with an aspheric focused lens. We can see typical signals from all 4 channels at 4 K, and obtain the positional dependence of the signal as the contour in XY plane. Our CB-KIDs can be used as neutron detectors by utilizing energy released from a nuclear reaction between ^{10} B and cold neutron.
    Journal of Low Temperature Physics 01/2014; 176(3-4). DOI:10.1007/s10909-014-1135-3 · 1.04 Impact Factor
  • IEICE Transactions on Electronics 01/2014; E97.C(3):132-140. DOI:10.1587/transele.E97.C.132 · 0.39 Impact Factor
  • IEICE Transactions on Electronics 01/2014; E97.C(3):188-193. DOI:10.1587/transele.E97.C.188 · 0.39 Impact Factor
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    ABSTRACT: We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.
    IEICE Transactions on Electronics 01/2014; E97.C(3):166-172. DOI:10.1587/transele.E97.C.166 · 0.39 Impact Factor
  • IEEE Transactions on Applied Superconductivity 01/2014; 25(3):1-1. DOI:10.1109/TASC.2014.2382973 · 1.32 Impact Factor
  • IEICE Transactions on Electronics 01/2014; E97.C(3):141-148. DOI:10.1587/transele.E97.C.141 · 0.39 Impact Factor
  • IEICE Transactions on Electronics 01/2014; E97.C(3):157-165. DOI:10.1587/transele.E97.C.157 · 0.39 Impact Factor
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    ABSTRACT: This paper describes the design and testing of an 8-bit asynchronous wave-pipelined sparse-tree RSFQ Arithmetic Logic Unit (ALU). Compared to previously developed RSFQ ALUs, this unit features an extensive set of 8 arithmetic and 12 logical operations. The execution of ALU operations consists of two steps. First, when necessary, one or both operands are inverted, and then operations are performed on these preprocessed data. Unlike the RSFQ Kogge-Stone-based designs, our parallel-prefix sparse-tree ALU has significantly reduced circuit complexity while maintaining robust operational margins at high frequency. An 8-bit ALU has been implemented with the ISTEC 10 kA/cm^2 1.0 μm 9-metal ADP2.1 fabrication process as a joint effort between Stony Brook University, Yokohama National University, and Nagoya University. Using the CONNECT cell library and SFQ CAD tools developed at Nagoya and Yokohama, the Stony Brook team has developed the complete logical and physical design of the ALU chip. The 8-bit ALU core (without SFQ-to-DC and DC-to-SFQ converters) consists of 8832 Josephson junctions with an area of 7.2 mm^2. Simulations show that the ALU can operate at the maximum rate of 42 GHz. It has the latency of 374 ps at a bias voltage of 2.5 mV. The chip was fabricated and tested at low frequency in 2012. Testing results showed malfunctioning of some gates but despite these shortcomings we still verified several ALU operations with the measured DC bias voltage margins of ±1.8%.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3). DOI:10.1109/TASC.2012.2229334 · 1.32 Impact Factor
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    ABSTRACT: We report successful operations of low-energy consumption rapid single-flux-quantum (RSFQ) circuits applying lowered driving voltages, called LV-RSFQ, using different fabrication processes. In the LV-RSFQ, we feed bias currents to Josephson junctions from lowered constant voltages (less than 1 mV) through small resistors without extra inductors. Both static and dynamic energy consumption are reduced because of suppression of amplitudes of SFQ pulses, in exchange for slower switching speed. We show that the switching speed in LV-RSFQ circuits is improved by increasing critical current density of Josephson junctions. We demonstrated high-speed operations of LV-RSFQ shift registers in a range of 5-40 GHz and 15-90 GHz using the 2.5-kA/cm2 and 10-kA/cm2 fabrication technologies, respectively. Comparison of the experimental results of the LV-RSFQ circuits fabricated using two different technologies derives the optimum bias voltage in terms of energy-delay product ranged from 0.1 to 1.0 ICRS, where ICRS is the product of Josephson critical current and shunt resistance.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3):1701104-1701104. DOI:10.1109/TASC.2013.2240555 · 1.32 Impact Factor
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    ABSTRACT: We will discuss the microarchitecture, design, and testing of the first 8 × 8-bit (by modulo 256) parallel carry-save RSFQ multiplier implemented using the ISTEC 10- kA/cm2 1.0-μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8 × 8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly regular layout with both local and global connections between modules. The multiplier core (without SFQ-to-DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm2 . The multiplier is designed with the target operation frequency of 20 GHz and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3):1300104-1300104. DOI:10.1109/TASC.2012.2227648 · 1.32 Impact Factor
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    ABSTRACT: In this paper, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor RSFQ adder implemented using ISTEC 10 kA/cm^2 ADP2.1 fabrication process. Compared to the Kogge-Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-DC and DC-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm^2. It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8% / -10.7%. Another adder chip consisting of 12785 junctions with additional on-chip circuits for 30 GHz testing was also fabricated but its testing showed the need for another fabrication run.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3). DOI:10.1109/TASC.2012.2233846 · 1.32 Impact Factor
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    ABSTRACT: We will discuss the microarchitecture, design, and testing of the first 8x8-bit (by modulo 256) parallel carry-save superconductor RSFQ multiplier implemented using the ISTEC 10 kA/cm^2 1.0 μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8x8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80 GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly-regular layout with both local and global connections between modules. The multiplier core (without SFQ-to- DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm^2. The multiplier is designed with the target operation frequency of 20 GHz, and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3). · 1.32 Impact Factor
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    ABSTRACT: We evaluated the relationship between the gray zone width and the operating margin for comparators composed of quasi-one-junction superconducting quantum interference devices (QOSs) with shunt resistors, which are often used as high-speed readout circuits in multiple superconductor detector systems. The gray zone width is a good measure of current sensitivity of a single-bit comparator. We numerically analyzed the gray zone width of a QOS comparator and determined the circuit parameters. The gray zone width obtained from the experiments concurred with the results of the numerical analysis and was 2--3 μA at 4.2 K in a QOS comparator composed of three Nb/AlOx/Nb junctions with critical currents of less than 90 μA. The experimentally obtained operating margin for the bias current provided to the comparator was ± 15% at the bias current of around 140 μA. These results show that QOS comparators are promising for readout circuits operating up to tens of GHz and imply that gray zone width is the thermal noise in the resistors at 4.2 K.
    Japanese Journal of Applied Physics 03/2013; 52(3):3101-. DOI:10.7567/JJAP.52.033101 · 1.06 Impact Factor
  • H. Akaike, T. Funai, S. Sakamoto, A. Fujimaki
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    ABSTRACT: We have evaluated the electrical characteristics of NbN/Al-AlNx/NbN tunnel junctions fabricated on sapphire-C or fused-silica substrates. NbN/Al-AlNx/NbN multilayers were prepared by reactive dc-magnetron sputtering deposition of lower and upper NbN layers, and rf-magnetron sputtering deposition of the Al layer, followed by radical-nitridation. The junctions showed low sub-gap leakage currents in the current-voltage characteristics at 4.2 K. The quality parameter, Rsg/Rn, where respective Rsg and Rn are the sub-gap resistance at 2 mV and junction resistance at 5 mV, was above 15. The gap voltage (Vg) was around 3.3 mV, which was reduced in comparison with Vg values of ~4.3 mV for junctions on MgO substrates. The reduced Vg was caused by superconducting properties of lower NbN layers deposited on the sapphire or fused-silica substrates. Uniformity in critical current (Ic) was relatively good, and the maximum-to-minimum spread in Ic was ±1.7% for 200 junctions on a sapphire substrate and ±2.0% for the junctions on a fused-silica substrate.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
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    ABSTRACT: We report experimental results of bit-error-rate (BER) measurements in small-critical-current or lowered-biasvoltage rapid single-flux-quantum (RSFQ) circuits for power reduction. In such reduced-power RSFQ circuits, the BERs can be increased because of the reduced signal-to-noise ratio. We fabricated 2-bit shift registers using a 2.5-kA/cm2 niobium process, and measured BERs by low-frequency tests at 4.2 K. We obtained sufficiently wide bias margins when we reduced the critical currents in a range of 1/2 to 1/4 of the conventional design, while it narrowed as the critical currents reduced to 1/8. For low-voltage shift registers, the bias margins linearly decreased in width as bias voltages were lowered. We found that 0.25 mV, 1/10 of the conventional design, was a good bias voltage to balance competing power reduction and bias margin.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
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    ABSTRACT: We present a new design technique of rapid single-flux-quantum (RSFQ) logic gates for low-noise, high-speed operation. In this study, we propose the use of a damping resistor shared with a junction pair composing a comparator, in addition to their individual shunt resistors increased from the standard values. We analyzed timing characteristics and bit error rates (BERs) of several RSFQ flip-flops composed of the proposed comparators using numerical simulation. The proposed comparator showed reduced timing jitter by ~5% in association with small delay time, sharpened BER curves, and improvement in operating margins by 2-3% compared to the standard design. We fabricated 2-bit shift registers using the noise reduction technique. We obtained sharp BER curves from the measurement. The proposed method indicated that it gave wide margins.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013

Publication Stats

1k Citations
299.06 Total Impact Points

Institutions

  • 1991–2014
    • Nagoya University
      • Department of Quantum Engineering
      Nagoya, Aichi, Japan
  • 2007–2009
    • Japan Science and Technology Agency (JST)
      Edo, Tōkyō, Japan
  • 2003–2007
    • Yokohama National University
      • Department of Physics, Electrical and Computer Engineering
      Yokohama-shi, Kanagawa-ken, Japan
  • 1998–2004
    • Kinki University
      • • Faculty of Biology-Oriented Science and Technology
      • • Department of Electronic System and Information Engineering
      Ōsaka, Ōsaka, Japan
  • 1995
    • Toyota National College of Technology
      Koromo, Aichi, Japan