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ABSTRACT: The feasibility of a high speed ferroelectric graphene memory device using a ferroelectric polymer (PVDF-TrFE)/graphene stack has been demonstrated. The conductivity of this metal-ferroelectric-graphene (MFG) device could be modulated up to 775% with a very fast programming speed down to 10 ns. Also, programmed states were maintained up to 1000 s with endurance over 1000 cycles. In addition to demonstrating a single memory device, the array-level integration and cell write/read functionality of a 4 × 4 MFG array adopting a graphene bit line has also been confirmed to show the feasibility of MFG memory.
Nanotechnology 04/2013; 24(17):175202. · 3.98 Impact Factor
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Chang Goo Kang,
Sung Kwan Lim,
Sangchul Lee,
Sang Kyung Lee,
Chunhum Cho, Young Gon Lee,
Hyeon Jun Hwang,
Younghun Kim,
Ho Jun Choi,
Sun Hee Choe,
Moon-Ho Ham,
Byoung Hun Lee
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ABSTRACT: The benefits of multi-layer graphene (MLG) capping on Cu interconnects have been experimentally demonstrated. The resistance of MLG capped Cu wires improved by 2-7% compared to Cu wires. The breakdown current density increased by 18%, suggesting that the MLG can act as an excellent capping material for Cu interconnects, improving the reliability characteristics. With a proper process optimization, MLG capped Cu interconnects could become a promising technology for high density back end-of-line interconnects.
Nanotechnology 03/2013; 24(11):115707. · 3.98 Impact Factor
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Chang Goo Kang,
Sang Kyung Lee, Young Gon Lee,
Hyeon Jun Hwang,
Chunhum Cho,
Sung Kwan Lim,
Jinseong Heo,
Hyun-Jong Chung,
Heejun Yang,
Sunae Seo,
Byoung Hun Lee
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ABSTRACT: Graphene has been considered as a candidate for interconnect metal due to its high carrier mobility and current drivability. In this letter, the breakdown mechanism of single-layer chemical-vapor-deposited (CVD) graphene and triple-layer CVD graphene has been investigated at three different conditions (air exposed, vacuum, and dielectric capped) to identify a failure mechanism. In vacuum, both single- and triple-layer graphenes demonstrated a breakdown current density as high as ~10<sup>8</sup> A/cm<sup>2</sup>, which is similar to that of exfoliated graphene. On the other hand, the breakdown current of graphene exposed to air was degraded by one order of magnitude from that of graphene tested in vacuum. Thus, oxidation initiated at the defect sites of CVD graphene was suggested as a major failure mechanism in air, while Joule heating was more dominant with dielectric capping and in vacuum.
IEEE Electron Device Letters 12/2011; · 2.85 Impact Factor
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Chang Goo Kang,
Jang Won Kang,
Sang Kyung Lee,
Seung Yong Lee,
Chun Hum Cho,
Hyeon Jun Hwang, Young Gon Lee,
Jinseong Heo,
Hyun-Jong Chung,
Heejun Yang,
Sunae Seo,
Seong-Ju Park,
Ki Young Ko,
Jinho Ahn,
Byoung Hun Lee
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ABSTRACT: A graphene nanoribbon (GNR) is an important basic structure to open a bandgap in graphene. The GNR processes reported in the literature are complex, time-consuming, and expensive; moreover, the device yield is relatively low. In this paper, a simple new process to fabricate a long and straight graphene nanoribbon with a high yield has been proposed. This process utilizes CVD graphene substrate and a ZnO nanowire as the hardmask for patterning. 8 µm long and 50-100 nm wide GNRs were successfully demonstrated in high density without any trimming, and ∼ 10% device yield was realized with a top-down patterning process. After passivating the surfaces of the GNRs using a low temperature atomic layer deposition (ALD) of Al(2)O(3), high performance GNR MOSFETs with symmetric drain-current-gate-voltage (I(d)-V(g)) curves were demonstrated and a field effect mobility up to ∼ 1200 cm(2) V(-1) s(-1) was achieved at V(d) = 10 mV.
Nanotechnology 07/2011; 22(29):295201. · 3.98 Impact Factor
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ABSTRACT: Device instabilities of graphene metal-oxide-semiconductor field effect transistors such as hysteresis and Dirac point shifts have been attributed to charge trapping in the underlying substrate, especially in SiO <sub>2</sub> . In this letter, trapping time constants around 87 μ s and 1.76 ms were identified using a short pulse current-voltage method. The values of two trapping time constants with reversible trapping behavior indicate that the hysteretic behaviors of graphene field effect transistors are due to neither charge trapping in the bulk SiO <sub>2</sub> or tunneling into other interfacial materials. Also, it is concluded that the dc measurement method significantly underestimated the performance of graphene devices.
Applied Physics Letters 06/2011; · 3.84 Impact Factor
