M. Soyuer

IBM, Armonk, New York, United States

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Publications (57)51.79 Total impact

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    ABSTRACT: This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.
    Canadian Journal of Physics 02/2011; 74(12):159-166. · 0.90 Impact Factor
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    ABSTRACT: A 10 Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12 μm CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.
    Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003; 10/2003
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    ABSTRACT: This paper reviews the key requirements for implementing such functions in monolithic form and describes their implementation in the IBM SiGe BiCMOS technology. Aspects focused on are the integration of 10--13-Gb/s serializer/deserializer chips with subpicosecond jitter performance, the realization of 40--56-Gb/s multiplexer/demultiplexer functions and clock-and-datarecovery /clock-multiplier units, and, finally, the implementation of some analog front-end building blocks such as limiting amplifiers and electro-absorption modulator drivers. Highlighted in this paper are the key challenges in mixed-signal and analog integrated circuit design at such ultrahigh data rates, and the solutions which leverage high-speed and microwave design and broadband SiGe technologies. 1.
    05/2003;
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    ABSTRACT: Considerable progress has been made in integrating multi-Gb/s functions into silicon chips for data- and telecommunication applications. This paper reviews the key requirements for implementing such functions in monolithic form and describes their implementation in the IBM SiGe BiCMOS technology. Aspects focused on are the integration of 10ߝ13-Gb/s serializer/deserializer chips with subpicosecond jitter performance, the realization of 40ߝ56-Gb/s multiplexer/demultiplexer functions and clock-and-data-recovery/clock-multiplier units, and, finally, the implementation of some analog front-end building blocks such as limiting amplifiers and electro-absorption modulator drivers. Highlighted in this paper are the key challenges in mixed-signal and analog integrated circuit design at such ultrahigh data rates, and the solutions which leverage high-speed and microwave design and broadband SiGe technologies.
    Ibm Journal of Research and Development 04/2003; · 0.69 Impact Factor
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    ABSTRACT: Silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BICMOS technology is a stable, ultra-high performance, semiconductor technology capable of supporting mixed-signal, very large-scale integration (VLSI) circuit designs for a variety of emerging communication applications. This technology is supported by a computer-aided design (CAD) system that supports a variety of high-performance circuit designs, mixed-signal circuit block reuse, and the ability to accurately predict circuit performance at the highest frequencies. This paper summarizes the progress this technology has made in recent years in moving from the research laboratory to a production environment. We also specifically address performance, operating voltage, reliability and integration considerations for using 100--200 GHz SiGe HBTs in high-speed (10--40 Gb/s) network ICs, an application space previously only addressed by InP technology. All indications are that SiGe will be very successful at addressing this new application space, and all facets of the networking IC market.
    Japanese Journal of Applied Physics 01/2002; 41:1111-1123. · 1.07 Impact Factor
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    ABSTRACT: The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q on the performance of radiofrequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5--100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q.
    05/2001;
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    ABSTRACT: SiGe BiCMOS technology provides a stable, ultra-high performance, semiconductor technology capable of supporting large mixed-signal VLSI circuit designs for a variety of emerging communications applications. This technology has been wedded to a CAD system that supports a variety of high-performance circuit designs, mixed-signal circuit block re-use, and the ability to accurately predict circuit performance at the highest frequencies. This paper will summarize the progress this technology has made in recent years in moving from the research laboratory into a production environment
    Custom Integrated Circuits, 2001, IEEE Conference on.; 02/2001
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    ABSTRACT: A fully integrated single-chip SiGe BiCMOS 12.5 Gbaud serializer/deserializer operates with sub-picosecond PLL jitter and error rates below 5e-14 with both transmit and receive channels active. The chip includes a 12.5 GHz clock multiplier, a 12.5 Gbaud clock and data recovery circuit, a 16:1 multiplexer, 1:16 demultiplexer, and integrated test features. The die area is 6.1 mm×6.1 mm and consumes 3.3 W from a 3.3 V supply in normal operating mode
    VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on; 02/2001
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    ABSTRACT: Two fully monolithic clock and data recovery (CDR) circuits for serial optical fiber links are presented. One CDR is targeting SONET OC-192 application while the other is a possible 10-GigaBit Ethernet application using 8B/10B coded data. The ICs are fabricated in a SiGe BiCMOS technology with a 45-GHz cut-off frequency. The CDRs extract a full rate clock and recover data from a random input bit stream. Each IC integrates a novel self-correcting phase detector, a delay-interpolating ring voltage-controlled oscillator, and a lock-to-reference loop for frequency acquisition. High-speed operation, low time jitter, and large jitter tolerance are the main features of the circuits. Each macro dissipates about 320 mW from 3.3-V supply
    IEEE Journal of Solid-State Circuits 01/2001; · 3.06 Impact Factor
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    ABSTRACT: Over the last decade, SiGe HBT BiCIMOS technology has matured from a laboratory research effort to become a 50/65-GHz fT/fmax silicon-based 0.5-μm BiCMOS production technology. This progress has extended silicon-based production technology into the multigigahertz (multi-GHz) and multigigabits-per-second (multi-Gb/s) range, thus, opening up an array of wireless and wired circuit and network applications and markets. SiGe circuits are now being designed in the same application space as GaAs MESFET and HBTs, and offer the yield cost, stability and manufacturing advantages associated with conventional silicon fabrication. A wide range of microwave circuits have been built in this technology including 5.8-GHz low-noise amplifiers with 1-V supply, up to 17-GHz fully monolithic VCOs with excellent figures of merit, high-efficiency 2.4-GHz power devices with supply voltage of 1.5 V, and move complicated functions such as 2.5/5.0-GHz frequency synthesizer circuits as well as 10/12.5-Gb/s clock and data recovery PLLs. This paper focuses on several key circuit applications of SiGe BiCMOS technology and describes the performance improvements that can be obtained by its utilization in mixed-signal microwave circuit design. By way of examples, the article highlights the fact that the combination of high-bandwidth, high-gain and low-noise SiGe HBTs with dense CMOS functionality in a SiGe BiCMOS technology enables implementation of powerful single-chip transceiver architectures for multi-GHz and multi-Gb/s communication applications
    Proceedings of the IEEE 11/2000; · 6.91 Impact Factor
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    M. Soyuer
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    ABSTRACT: Not Available
    Solid-State Device Research Conference, 2000. Proceeding of the 30th European; 10/2000
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    ABSTRACT: This work demonstrates the effect of substrate loss, efficiency, and frequency response of the three generic spiral-coil transformers: stacked, bifilar and nested. The dependence of loss on the spacing of transformer coils from the oxide-silicon interface is confirmed experimentally. The high gains and better-than-expected bandwidths of the stacked transformers as compared to those of the bifilar and nested transformers are demonstrated. The effect of bulk silicon on transformer efficiency is investigated with the use of a substrate transfer technique
    Silicon Monolithic Integrated Circuits in RF Systems, 2000. Digest of Papers. 2000 Topical Meeting on; 02/2000
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    ABSTRACT: A fully integrated and differential SiGe VCO was designed for 5 GHz wireless applications. The measured phase noise is -98 dBc/Hz at 100 kHz offset off the 5 GHz carrier. It has a tuning range of 12.3% with a control voltage from 0 to 3 V, and a figure of merit of more than -180 dBc/Hz, The current drawn from 3 V is 5 mA for the core and 2.2 mA for the output buffers
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2000. Digest of Papers. 2000 IEEE; 02/2000
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    ABSTRACT: A 9.95 Gb/s and a 12.5 Gb/s fully-monolithic 3.3 V clock and data recovery (CDR) circuit, are targeted at SONET OC-192 and 10GBE applications, respectively. The ICs are implemented in a production level SiGe BiCMOS with 45 GHz cut-off frequency. Compared to other technologies for high-speed ICs, such as GaAs HBT technology, SiGe BiCMOS technology has advantages. It provides a much higher integration density and enables the combination of very complex digital functions with multi-gigabit digital/analog functions on the same chip, providing cost-effective and smart solutions for complex communication systems. Several CDR circuits at 10 Gb/s using SiGe and Si technology are recently reported
    Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International; 02/2000
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    ABSTRACT: Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10 Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5 GHz clock with 0.4 ps rms jitter synthesized from a ~195.3 MHz reference. The receive PLL (RxPLL), which exhibits <0.56 ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5 Gb/s input bit stream. The RxPLL operates error-free when tested with a 14 km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3 V are 270 mW and 330 mW, respectively
    VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
  • H. Ainspan, M. Soyuer
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    ABSTRACT: This paper presents a 20-channel, 4.850-5.325 GHz PLL-based frequency synthesizer implemented in a production SiGe BiCMOS technology. The circuit is fully integrated, including the loop filter capacitor and VCO. A fast settling time of 10 μs is measured with a reference frequency of 12.5 MHz. Wafer-level tests indicate a phase noise below -100 dBc/Hz at a 1 MHz offset. The chip dissipates 255 mW from a 3.3 V supply and occupies an active area of 2 mm<sup>2</sup>
    Bipolar/BiCMOS Circuits and Technology Meeting, 1999. Proceedings of the 1999; 02/1999
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    ABSTRACT: A 5.2 GHz I/Q RF transceiver using a 0.5-μm SiGe BiCMOS technology is designed and measured. The receiver exhibits a 11.7 dB down-conversion gain, a DSB noise figure of 7.5 dB, an input IP3 of -11.2 dBm, and an amplitude imbalance of 0.33 dB for a 300 MHz IF. For the transmitter an up-conversion gain of 14.7 dB, an output 1 dB compression point of -23 dBm, an amplitude imbalance of 0.5 dB, and a 7 GHz 3 dB bandwidth were measured. The power consumption is 122 mW for the receiver and 114 mW for the transmitter at 3.3 V power supply
    Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999; 02/1999
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    ABSTRACT: A 5.2 GHz RF transmitter using a 0.5-¿m SiGe BiCMOS technology is designed and measured. The IC contains an up-conversion mixer, a power-amplifier driver, a fully monolithic VCO and digital frequency divider. The transmitter exhibits a 24 dB up-conversion power gain with a flatness of ±0.65 dB over a 750 MHz bandwidth, and an output 1-dB compression of + 1 dBm for a total power consumptdon of 126 mW at 3.3V power supply.
    01/1999;
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    ABSTRACT: The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q an the performance of radio-frequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5-100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q
    IEEE Journal of Solid-State Circuits 01/1999; · 3.06 Impact Factor
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    ABSTRACT: A 5.5-GHz low-noise amplifier (LNA) with switchable gain and temperature and supply-voltage compensation implemented in SiGe BiCMOS is presented. The LNA gain (S 21 ) and 50-Ω noise figure are 14.1 dB and 2.4 dB, respectively, at 25°C. An on-chip proportional-to-absolute temperature (PTAT) current reference reduces the variation in S 21 and NF 50Ω to 0.35 dB and 0.5 dB, respectively, from 0 to 100°C. The input third-order intermodulation intercept is +1.4 dBm. The circuit consumes 4.7 mA total current from a 2.5-V supply.
    Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European; 10/1998