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ABSTRACT: Sequence alignment is an essential, but compute-intensive application in Bioinformatics. Hardware implementation speeds up this application by exploiting its inherent parallelism, where the performance of the hardware depends on its capability to align long sequences. In hardware terms, the length of a biological query sequence that can be aligned against a database sequence depends on the number of Processing Elements (PEs) available, which in turn depends on the amount of available hardware resources. In addition, the amount of available bandwidth to transfer the data processed by these PEs plays a significant role in defining the maximum performance. In this paper, we carry out a detailed performance and bandwidth analysis for biological sequence alignment and formulate theoretical performance boundaries for various cases. Further, we optimize the performance gain and memory bandwidth requirements and develop generalized equations for this optimization.
Design and Test Workshop (IDT), 2010 5th International; 01/2011
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ABSTRACT: The fault coverage of otherwise efficient memory tests can be dramatically reduced due to the influence of bit line coupling. This paper, analyzes the impact of parasitic bit line coupling and neighborhood coupling data backgrounds on the faulty behavior of SRAMs. It investigates and determines the worst case coupling backgrounds required to induce worst case coupling effects, and validates the analysis through defect injection and circuit simulation of all possible spot defects in the SRAM cell array. The paper clearly demonstrates the inadequacies and limitations of several industrial tests in detecting memory faults in the presence of bit line coupling. Finally, it shows how to detect all single-cell and two-cell faults, both in the absence and in the presence of bit line coupling for any possible spot defect.
Test Conference (ITC), 2010 IEEE International; 12/2010
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ABSTRACT: In this paper, we present a novel method based on hardware partitioning to reduce the execution time and improve the resource utilization of biological sequence alignment, resulting in a higher performance as compared to conventional approaches. The paper shows that the method reduces the execution time and improves the resource utilization up to 33.3%. Further, equations are derived, showing the general trend of execution time reduction, resource utilization improvement and hence performance enhancement.
Engineering in Medicine and Biology Society (EMBC), 2010 Annual International Conference of the IEEE; 10/2010
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ABSTRACT: Due to the decreasing dimensions of manufactured devices, the effect of bit line capacitive coupling on the behavior of faulty memory cells cannot be ignored. Neighboring cells influence the faulty behavior of defective cells through coupling. This paper analyzes and validates this behavior theoretically and through electrical simulations. The paper evaluates the impact of bit line coupling in SRAMs on cell faulty behavior and identifies necessary conditions to induce worst-case coupling effects. We present a test that guarantees detecting all single-cell static faults in the presence of capacitive coupling and worst-case neighborhood data for any possible open defect.
VLSI Test Symposium (VTS), 2010 28th; 05/2010
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ABSTRACT: Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect ADDFs; the paper also shines a new light on the use of the different stress combinations (counting methods, data-backgrounds) and their importance for the detection of ADDFs. Second, it provides an improved algorithm for detecting BLIFs; it increases the defect coverage by being able to detect lower leakage currents.
Asian Test Symposium, 2009. ATS '09.; 12/2009
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ABSTRACT: Stress optimization for memory devices is a complex process due to the continuous space of possible optimization values for relevant parameters. This paper uses a method based on electrical Spice simulation to perform this optimization process for DRAM devices. The paper presents a case-study performed in Qimonda to optimize the timing and temperature stresses for the strap problem in defective memory cells. The paper also considers the impact of bit line coupling effects on the faulty behavior and identifies the worst case coupling background needed to detect the faulty cells.
Design and Test Workshop (IDT), 2009 4th International; 12/2009
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ABSTRACT: In this paper, we present an efficient and high performance linear recursive variable expansion (RVE) implementation of the Smith-Waterman (S-W) algorithm and compare it with a traditional linear systolic array implementation. The results demonstrate that the linear RVE implementation performs up to 2.33 times better than the traditional linear systolic array implementation, at the cost of utilizing 2 times more resources.
Engineering in Medicine and Biology Society, 2009. EMBC 2009. Annual International Conference of the IEEE; 10/2009
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ABSTRACT: Almost all manufacturing memory test programs use the time-efficient Scan test to screen the defective chips in an early stage. Usually, Scan is used to screen out the easy-to-detect hard faults like stuck-at-faults. In this paper we will show how Scan can be modified to increase the fault coverage and detect unique faults. It will be shown that many additional faults are detectable using Scan if appropriate read-write sequence, an appropriate data-background and appropriate addressing method are used. Such additional faults consist not only of static/traditional faults, but also of dynamic and time-related faults which are of increasing importance with the technology scaling. Examples of such faults are dynamic faults in the peripheral circuits (e.g., sense amplifiers, pre-recharge circuits, etc) and in the address decoders. Industrial results are presented to validate the proposed approach.
Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on; 05/2009
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ABSTRACT: This paper presents an analysis, at the electrical level, of address decoder faults caused by resistive opens within (a) dynamic address decoders and (b) static address decoders, which have special circuits that deactivate them at fixed moment. Efficient algorithms are proposed to cover the targeted faults. DFT circuit, to facilitate the BIST implementation of the proposed tests, is also provided. Furthermore, the limitations of the current/existing approaches in detecting delay faults are addressed.
Design and Test Workshop, 2008. IDT 2008. 3rd International; 01/2009
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ABSTRACT: In this paper we adapted a novel approach for accelerating the Smith-Waterman (S-W) algorithm using Recursive Variable Expansion (RVE), which exposes extra parallelism in the algorithm, as compared to any other technique. The results demonstrate that applying the recursive variable expansion technique speeds up the performance by a factor of 1.36 to 1.41, as compared to traditional acceleration approaches at the cost of using 1.25 to 1.28 times more hardware resources.
Design and Test Workshop, 2008. IDT 2008. 3rd International; 01/2009
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ABSTRACT: The faulty behavior of memory devices has traditionally been evaluated in isolation of the parasitic effects present on chip. As these effects become more dominant, however, they start to negatively influence the fault coverage of commonly used memory tests. This paper studies the way bit line coupling affects the faulty behavior of SRAM devices. Spice simulations are used to show how coupling can prevent the detection of otherwise detectable faults. Furthermore, an evaluation is done of the needed bit line coupling conditions to guarantee a high fault coverage of a given defect. This is done by identifying the most stressful data background patterns in the neighborhood of the faulty cell.
Design and Test Workshop, 2008. IDT 2008. 3rd International; 01/2009
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ABSTRACT: The continued increase of the integration density of systems on chip (SoCs) and the number of embedded memory blocks in them, together with the continued technology scaling, increases their sensitivity to a variety of potential manufacturing (new) defects. Standard march tests are usually used to achieve a good fault/defect coverage. This paper presents an experiment in diagnosing defects in the circuitry responsible for the realization of bit, byte or group write enable in memories. First defects in such circuitry are analyzed, and fault models together with an appropriate test algorithm are presented. Subsequently, the test is added to an existing BIST engine to target the bit/byte write enable faults. The preliminary silicon results of two experiments are presented. They validate some of the targeted fault models and show the importance of considering bit/byte write enable faults for high outgoing product quality.
Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on; 12/2008
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ABSTRACT: Efficient and effective methods are needed to generate defect oriented tests for todays VLSI circuits. This paper describes an industrial case study for using defect injection and Spice simulation to generate defect oriented tests for the so-called strap defects in DRAMs, taking both the sensitivity of this defect to process variations and bit line coupling into consideration. The paper discusses all the different stages of the test generation process, starting with defect modeling, followed by the simulation methodology, test generation and optimization, and finally test application and industrial evaluation performed in Qimonda. Results show that the generated tests have the same coverage as previously used tests with possible test time reduction of up to 59%. The analysis also identifies the slow process corner and the data backgrounds 11 and 01 as the most stressful combinations to test the strap. The paper also discusses a test method used to account for process variations and detect the fault in any process corner.
Test Conference, 2008. ITC 2008. IEEE International; 11/2008
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ABSTRACT: Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize the test set used at Intel to test their 512-kB caches manufactured in a 0.13- mum technology. An example is shown where a maximal test set of 15 tests with a corresponding maximum test time of 160.942 ms/chip is optimized to only six tests that require a test time of only 30.498 ms/chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 07/2008; · 1.22 Impact Factor
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ABSTRACT: In this paper, a complete analysis of address decoder delay faults due to capacitive coupling between address lines is presented. Detection conditions are used to explore the space of possible tests in order to detect these faults, resulting in new tests. The best test is proposed to be combined with other tests (while using the freedom of march tests) to target other faults.
Design and Test Workshop, 2007. IDT 2007. 2nd International; 01/2008
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ABSTRACT: Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: under specification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.
Design and Test Workshop, 2007. IDT 2007. 2nd International; 01/2008
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ABSTRACT: Sequence alignment is one of the most important activities in bioinformatics. With the ever increasing volume of data in bioinformatics databases, the time for comparing a query sequence with the available databases is always increasing. Many algorithms have been proposed to perform and accelerate sequence alignment activities. This paper introduces a taxonomy of the various sequence alignment algorithms found in the literature, with particular emphasis on the Smith-Waterman (S-W) algorithm. The paper also provides a classification of the available hardware acceleration methods used to speed up the S-W algorithm.
Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on; 10/2007
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ABSTRACT: As the complexity of memory faulty behavior increases, it is becoming more difficult to precisely identify the faults the memory exhibits. Knowledge of the precise set of faults is essential for designing an optimal set of memory tests with low test time and high fault coverage. This paper presents an automatic method to analyze the observed faulty behavior and to map it precisely into corresponding faults. The method is unique in its generality, making it possible to identify both static as well as dynamic faults in the behavior. Depending on the complexity of the performed fault analysis, different algorithms may be used, with increasing level of computational complexity.
Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on; 10/2007
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ABSTRACT: High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result in their own set of faults, and increase the complexity of already known faults. This paper describes the influence of bit line coupling on precharge faults, where the memory is rendered unable to set the proper precharge voltages at the end of each operation, which causes the memory to fail in subsequent read operations. This kind of bit line coupling effect on precharge behavior has been observed in high speed DRAMs at Qimonda. This paper gives a detailed analysis of the problem, and suggests effective tests to detect it. The paper also describes the results of an industrial test evaluation on actual DRAMs chips, performed to validate the effectiveness of the proposed tests.
Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE; 05/2007
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ABSTRACT: This paper presents a complete electrical analysis of address decoder delay faults "ADFs" caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests
IEEE Transactions on Computers 01/2007; 55(12):1630-1639. · 1.10 Impact Factor
