R.W. Dutton

Stanford University, Stanford, CA, United States

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Publications (318)341.72 Total impact

  • Source
    E. Pop · Chi On Chui · R. Dutton · S. Sinha · K. Goodson
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    ABSTRACT: This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We introduce a self-consistent model for calculating device temperature, saturation current and intrinsic gate delay. We show that the raised device source/drain can be designed to simultaneously lower device temperature and parasitic capacitance, such that the intrinsic gate delay (CV/I) is optimal. We find that a raised source/drain height approximately 3 times the channel thickness would be desirable both from an electrical and thermal point of view. Optimized GOI devices could provide at least 30 percent performance advantage over similar SOI devices, despite the lower thermal conductivity of the germanium layer.
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
  • Source
    Chang-Hoon Choi · Jung-Hoon Chun · Robert W. Dutton
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    ABSTRACT: The electrothermal characteristics of strained-Si MOSFETs, operating in the high-current regime, have been studied using device simulation. The phonon mean-free-path of strained-Si devices in the presence of high electric fields is determined, based on fullband Monte Carlo device simulation. Strained-Si nMOS devices have higher bipolar current gain and impact ionization rates compared to bulk-Si nMOS devices due to the smaller energy bandgap and longer phonon mean-free-path. Even though strained-Si devices have self-heating problems due to the lower thermal conductivity of the buried SiGe layer, the devices can be used beneficially for electrostatic discharge protection devices to achieve lower holding voltage (V<sub>h</sub>) and higher second breakdown triggering current (I<sub>t2</sub>), compared to those of bulk-Si devices, owing to the high bipolar current gain and current uniformity.
    IEEE Transactions on Electron Devices 12/2004; 51(11-51):1928 - 1931. DOI:10.1109/TED.2004.836542 · 2.47 Impact Factor
  • C. Jungemann · B. Neinhus · B. Meinerzhagen · R.W. Dutton
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    ABSTRACT: A comprehensive investigation of the SPICE and unified compact noise models is performed by comparison with the more fundamental hierarchical hydrodynamic device model. It is shown that the rather simple SPICE and unified compact noise models yield good results for frequencies up to 10 GHz for state-of-the-art SiGe HBTs with a low base resistance. The base noise resistance, a key parameter of the compact noise models turns out to be independent of frequency and bias. It can be well estimated based on the sheet resistance of the intrinsic and extrinsic base or with the modified circle-fit method. The unified model, which in comparison to the SPICE model considers in addition the finite transit time of shot noise, is found to be somewhat more accurate than the SPICE model, especially at higher frequencies and collector currents. But this is achieved at the expense of a transit time parameter which cannot be determined without accurate and detailed noise measurements or physics-based numerical simulations.
    IEEE Transactions on Electron Devices 07/2004; 51(6-51):956 - 961. DOI:10.1109/TED.2004.828277 · 2.47 Impact Factor
  • Source
    Jung-Hoon Chun · C. Duvvury · G. Boselli · H. Kunz · R.W. Dutton
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    ABSTRACT: A new failure mechanism of PMOSFET devices under ESD conditions is reported and analyzed by investigating various I/O structures. Localized turn-on of the parasitic pnp transistor can be caused by localized charge injection into the body of the PMOSFET. Critical layout parameters affecting this problem are discussed based on 2-D device simulations. A general strategy for avoiding this failure mode is also suggested.
    Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
  • Source
    H. Lan · R. Dutton
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    ABSTRACT: An approach for synthesized compact models (SCM) of substrate noise coupling is presented. The model is formulated using parameterized and scalable Z matrix. The improvement in modeling near field effects results in better substrate noise modeling for analog circuits. The geometrical scalability of the model provides a bi-directional link between noise analysis in the post-layout phase for verification and the noise-aware layout synthesis using convex optimization techniques. The model is validated by rigorous EM and device simulations. Several application examples are used to demonstrate the bi-directional usage of the model.
    Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings; 03/2004
  • Source
    G. Veronis · Yi-Chang Lu · R.W. Dutton
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    ABSTRACT: A new full-wave method is introduced for substrate noise analysis and simulation. The method is based on solution of the wave equation for the magnetic potential and can be implemented using standard circuit simulators. We compare the new method with the standard quasi-static method for typical substrate profiles and investigate the limits of validity of the quasi-static method.
    Quality Electronic Design, 2004. Proceedings. 5th International Symposium on; 02/2004
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    ABSTRACT: The first hydrodynamic RF noise model for CMOS devices including a consistent set of quantum correction and mobility models for the inversion layer is presented. Good agreement of simulations and recent noise measurements for deep sub-micron devices is obtained. In the case of classical and non-classical CMOS devices with channel lengths of 50 nm it is found that the drain excess noise factor is still below two and the increase in drain noise for short channel devices is therefore not as dramatic as previously reported.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
  • Source
    E. Pop · R. Dutton · K. Goodson
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    ABSTRACT: This paper explores the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices. A compact thermal model is introduced, incorporating the most advanced understanding of nanoscale heat conduction available. Novel device scaling is analyzed from a thermal point of view. We show device temperatures are very sensitive to the choice of drain and channel extension dimensions, and suggest a parameter design space which can help alleviate thermal problems. ITRS power guidelines below the 25 nm technology node should be revised if isothermal scaling of thin-body devices is desired.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
  • Source
    Jung-Hoon Chun · Yang Liu · C. Duvvury · R.W. Dutton
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    ABSTRACT: The specific contact resistance (ρ<sub>c</sub>) at the metal/semiconductor interface is known to be a monotonically decreasing function of temperature. Therefore the temperature dependence of ρ<sub>c</sub> has significant implications for the reliable electrothermal behavior of deep submicron devices under high current and high temperature conditions. In this work, the effect of contact resistance on the performance of ESD protection devices has been investigated by device simulation and experiment with test structures in a 0.13 μm silicided CMOS process. A temperature-dependent model for ρ<sub>c</sub> was implemented in a device simulator; results based on the new model are presented in comparison with results of a self-consistent Schottky diode model which unifies thermionic emission and tunneling effects.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
  • Source
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    ABSTRACT: Historically, analog models and the simulators in which they are embedded form a single analog simulation kernel. This was true of SPICE and its predecessors and is true of most commercial and proprietary analog simulators in use today. As a consequence, while model interfaces generally serve the same function (allowing the model to define the differential equations of a system), the mechanics of each interface is specific to its simulator and the interface is complex and tightly interwoven with the analysis engine. Adding a new model to any analog simulator is a task that is measured in engineer-months requiring intimate knowledge of the simulator's architecture and, in some cases, thousands of lines of C code (BSIM4 is ~15k lines in SPICE3). Verilog-A, a language originally intended for behavioral modeling, has been shown to be a viable alternative to C-code [1-3] with comparable implementations typically providing an order of a magnitude reduction in the number of lines of code necessary. Acceptance of a model requires its availability in main-stream simulators. Simulation vendors generally do not add unproven, immature models because the return on investment is never guaranteed. For these reasons the cycle of analog model development and maturation has never flourished in analog CAD – an area of CAD where perhaps having accurate predictive models is most crucial. The capability of Verilog-A to describe compact model behavior in a concise and portable fashion can only be realized if commercial simulators incorporate the interface in a consistent way. In this paper we present simulation results using a new modular architecture implemented in both commercial and research simulators. We use industry standard models, including BSIMSOI and BSIM3, as well as MEMS models coupled into complex harmonic balance and device level simulators. This is the first demonstration of multiple commercial simulators sharing the same model binaries.
  • Source
    Chang-Hoon Choi · Zhiping Yu · R.W. Dutton
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    ABSTRACT: Gate tunneling current in fully depleted, double-gate (DG) silicon-on-insulator (SOI) MOSFETs is characterized based on quantum-mechanical principles. The gate tunneling current for symmetrical DG SOI with ground-plane (t<sub>ox</sub> = 1.5 nm and T<sub>SI</sub> = 5 nm) is shown to be higher relative to single-gate (bulk) MOS structure. The tunneling is enhanced as the silicon layer becomes thinner since the thinner silicon layer acts a deep quantum well. The simulated I<sub>G</sub>-V<sub>G</sub> of DG SOI has negative differential resistance like that of the resonant tunnel diodes at the gate bias ∼ 1.4 V.
    IEEE Transactions on Electron Devices 01/2004; 50(12-50):2579 - 2581. DOI:10.1109/TED.2003.920126 · 2.47 Impact Factor
  • Source
    Reza Navid · Thomas H. Lee · R.W. Dutton
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    ABSTRACT: The fundamental question of how much we can ultimately reduce the phase noise of a lumped, inductorless oscillator through careful design is addressed and it is shown that the fluctuation dissipation theorem of thermodynamics imposes a lower limit on the phase noise. An analytical formulation of this limit is presented and it is shown that the phase noise of ring oscillators with long-channel MOS devices is closer to this limit compared to that of the relaxation oscillators or ring oscillators with short channel MOS devices.
    Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003; 10/2003
  • Source
    L.M. Hillkirk · Jung-Hoon Chun · R.W. Dutton
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    ABSTRACT: Transient device simulations reproducing conditions similar to Electro-Static Discharge (ESD) conditions have been performed for the entire safe operating area (SOA) of a 0.13 μm technology, ground-gated N-channel Metal-Oxide-Semiconductor (ggNMOS) transistor up to 2<sup>nd</sup> breakdown, using a set of macroscopic physical models related to previous studies implemented in MEDICI. The simulations results indicate the potential influence of a source-end mechanism of destruction, in addition to the previously reported drain-end avalanche generation of electron-hole pairs and subsequent thermal runaway in the proximity of the carriers generation spot as a result of the large carrier density. Under dynamic conditions and with non-zero contact resistance, thermal runway is also observed on the source-side of the device indicating that, for values of the contact resistance on the order of 5.4e<sup>-6</sup> Ohms-cm<sup>2</sup>, substantial damage can occur at the source end. The simulation results are in qualitative agreement with experimental results where it is observed that, after electrical and subsequent thermal runaway, damage is localized not only at the drain region but also at the source region of the device. Thus, the ESD related destruction of a 0.13 μm gate ggNMOS may not be the result of a single destruction mechanism, but the consequence of coupled events, depending on the design characteristics of a particular device.
    Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on; 10/2003
  • Source
    Tae-young Oh · C. Jungemann · R.W. Dutton
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    ABSTRACT: A noise model for MOSFETs based on analytical microscopic noise sources has been developed and noise simulations based on the hydrodynamic model have been performed. The drain and gate excess noise parameters and correlation coefficient are extracted and the reasons for noise parameter dependence on the channel length are explained.
    Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on; 10/2003
  • Source
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    ABSTRACT: Degraded junction leakage current in scaled MOSFETs due to enhanced band-to-band tunneling (i.e. local Zener effect) is characterized based on a modified band-to-band tunneling model. To suppress the severe drain leakage current in the presence of high-dose halo implants, the impact of implant conditions on drain leakage current is estimated based on implant induced damage (point defect) profiles.
    Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on; 10/2003
  • Source
    Eric Pop · R. Dutton · Kenneth E. Goodson
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    ABSTRACT: As current device technologies advance into the sub-continuum regime, they operate at length scales on the order of the electron and phonon mean free path. The ballistic conditions lead to strong non-equilibrium at nanometer length scales. The electron-phonon interaction is not energetically or spatially uniform and the generated phonons have widely varying contributions to heat transport. This work examines the microscopic details of Joule heating in bulk silicon with Monte Carlo simulations including acoustic and optical phonon dispersion. The approach provides an engineering tool for electro-thermal analysis of future nano-devices.
    Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on; 10/2003
  • Jaejune Jang · Zhiping Yu · R.W. Dutton
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    ABSTRACT: An accurate method to extract a small signal equivalent circuit model of RF silicon MOSFETs is presented. Analytical calculations are used for each intrinsic parameter and accuracy is within 1% for the entire operational region. 2D physical device simulation is used to analyze this methodology. A simple non-quasi static (NQS) model is reported, which offers good accuracy needed for circuit simulation, including a simple network representing the coupling between source and drain. Accurate extraction methods for extrinsic parameters have been also developed. The compact model and its parameter extraction are verified on Si-MOSFETs through S-parameter measurements.
    Microwave Symposium Digest, 2003 IEEE MTT-S International; 07/2003
  • Source
    Chang-Hoon Choi · Zhiping Yu · Robert W. Dutton
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    ABSTRACT: The distortion behavior for thin oxide MOS transistors can be degraded due to polysilicon-gate depletion effects. The nonlinear, bias-dependent gate capacitance for thin oxide MOSFET's results in significant 2nd-order derivatives in gate capacitance, (/spl part//sup 2/C(V/sub gs/)//spl part/V/sub gs//sup 2/), which in turn results in substantial 3rd-order derivative contributions to drain current, (/spl part//sup 3/I/sub ds///spl part/V/sub gs//sup 3/). This may restrict the use of very-thin oxide MOSFET's in RF applications.
    IEEE Electron Device Letters 06/2003; 24(5-24):330 - 332. DOI:10.1109/LED.2003.812549 · 2.75 Impact Factor
  • Source
    Hai Lan · Zhiping Yu · R.W. Dutton
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    ABSTRACT: A simple, efficient CAD-oriented equivalent circuit modeling approach of frequency-dependent behavior of substrate noise coupling is presented. It is shown that the substrate exhibits significant frequency-dependent characteristics for high frequency applications using epitaxial layers on a highly doped substrate. Using the proposed modeling approach, circuit topographies consisting of only ideal lumped circuit elements can be synthesized to accurately represent the frequency response using y-parameters. The proposed model is well-suited for use in standard circuit simulators. The extracted model is shown to be in good agreement with rigorous 3D device simulation results.
    Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on; 04/2003
  • Zhiping Yu · D. W. Yergeau · R.W. Dutton
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    ABSTRACT: An accurate and general algorithm for evaluating vector quantities, such as electric field, at the nodes in a finite volume discretization is presented. The algorithm is based on the integral form of Poisson's and the carrier continuity equations. Application to the analysis of sub-50nm MOSFETs with quantum mechanical (QM) effects is demonstrated. Other applications include the coupled electrothermal simulation (Joule heat) and modeling of impact ionization.
    VLSI Technology, Systems, and Applications, 2003 International Symposium on; 02/2003

Publication Stats

5k Citations
341.72 Total Impact Points


  • 1977–2011
    • Stanford University
      • • Center for Integrated Systems
      • • Department of Electrical Engineering
      • • Department of Applied Physics
      Stanford, CA, United States
  • 2009
    • University of Vienna
      • Faculty of Mathematics
      Vienna, Vienna, Austria
  • 2008
    • University of Texas at Austin
      Austin, Texas, United States
  • 2002–2008
    • Advanced Micro Devices
      Sunnyvale, California, United States
  • 2007
    • University of California, Santa Cruz
      Santa Cruz, California, United States
    • Rambus
      Sunnyvale, California, United States
  • 2005
    • Infineon Technologies
      München, Bavaria, Germany
  • 2004
    • Technische Universität Braunschweig
      Brunswyck, Lower Saxony, Germany
  • 2001
    • Mission College
      Santa Clara, California, United States
    • United States Naval Research Laboratory
      Washington, Washington, D.C., United States
  • 1997
    • Hewlett-Packard
      Palo Alto, California, United States
  • 1994
    • Seoul National University
      • Department of Electrical and Computer Engineering
      Seoul, Seoul, South Korea
  • 1992
    • Lafayette College
      Easton, Pennsylvania, United States
  • 1990–1992
    • University of California, Berkeley
      Berkeley, California, United States
  • 1991
    • Lawrence Livermore National Laboratory
      Livermore, California, United States
  • 1985
    • CA Technologies
      New York, New York, United States