R.W. Dutton

Stanford University, Palo Alto, California, United States

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Publications (419)430.86 Total impact

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    A. Hassibi, Yang Liu, R.W. Dutton
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    ABSTRACT: Scaling of devices in the semiconductor industry has reached an extremely impressive level; electronic device dimensions are approaching atomic scales and can also have dimensions comparable to many biological microstructures. In this paper, we present an overview of the new challenges in modeling electronics that interface with and bridge into the domains of biotechnology. In particular, we will discuss the applications of conventional integrated circuits technology computer-aided design (TCAD) in these new and emerging areas. Furthermore, we will examine the unique modeling requirements of biosensors in molecular identification and quantification applications. As we will discuss in this paper, there are exciting research challenges for the electronics community - new opportunities to leverage lessons learned from scaling.
    Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on; 10/2008
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    ABSTRACT: This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45 nm silicon on insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.
    Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th; 10/2008
  • Tze Wee Chen, A. Wallash, R.W. Dutton
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    ABSTRACT: For the first time, damage thresholds for TMR and GMR read sensors were measured using pulses with widths ranging from 40 ps to 2.3 ns. The ultra-fast pulses were generated using a novel Ultra-Fast Transmission Line Pulsing (UFTLP) system. The damage voltage level for the TMR and GMR heads was about 0.6 V using 2.3 ns-wide pulses, and increased to about 2.0 V using 40 ps-wide pulses. However, the damage current level for the TMR design was about 4 mA, about an order of magnitude lower than the GMR design. It is important to measure the failure level using pulses with pulse widths less than 1 ns wide because write-to-read crosstalk can produce such transients during writing. It is concluded that damage to the reader from 500 ps-wide write-to-read crosstalk transients will occur if it exceeds approximately 1 V.
    Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th; 10/2008
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    ABSTRACT: Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si<sub>0.7</sub>Ge<sub>0.3</sub>/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices.
    IEEE Transactions on Electron Devices 08/2008; DOI:10.1109/TED.2008.925329 · 2.36 Impact Factor
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    Yang Liu, Jon Sauer, Robert W. Dutton
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    ABSTRACT: A numerical study within the framework of the Poisson–Nernst–Planck equations is conducted to investigate electrostatic screening of charged biomolecules within synthetic pores having diameters of at least 10 Debye lengths. We show that with external biases, the biomolecule charge is only partially screened due to the presence of electro-diffusion current flow. This is considerably different from the equilibrium Debye–Huckel screening behavior and will result in long-range electrostatic interactions. The potential application to direct biomolecule charge sensing is also discussed.
    Journal of Applied Physics 04/2008; 103(8):084701-084701-4. DOI:10.1063/1.2906327 · 2.19 Impact Factor
  • P. Nikaeen, B. Murmann, R.W. Dutton
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    ABSTRACT: A 4-bit flash ADC is investigated in presence of substrate noise generated by switching activities in digital blocks. The impact of noise is analyzed in different building blocks of the ADC and is measured experimentally using a high-speed ADC test block fabricated in a 0.18-mum SiGe BiCMOS process. Measurement results show that noise spikes in the substrate cause distortion in the prototype ADC and degrade its SNDR by 2 dB (10%) at noise frequencies above 200 MHz.
    Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on; 04/2008
  • Jae Wook Kim, B. Murmann, R.W. Dutton
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    ABSTRACT: Low-voltage hybrid silicon-germanium bandgap reference circuits that can defy the voltage scaling limits of those realized in purely silicon-based technologies are implemented. Germanium diodes replace silicon diodes in two conventional bandgap reference circuits fabricated in a 0.18-mum Si CMOS process, and experimental results validate the benefit of exploiting a low bandgap material. The output references are measured as 670 mV and 310 mV with 9.3 mV (287 ppm/degC) and 4.6 mV (302 ppm/degC) variation, respectively, over 5 ~ 56degC. In addition, the high temperature characteristics limiting the operation range related to low bandgap are investigated.
    Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on; 04/2008
  • Jongchol Kim, Chia-Yu Chen, Robert W. Dutton
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    ABSTRACT: An effective algorithm for a one dimensional Schrödinger solver is proposed. The algorithm is derived from Bohm’s form of Schrödinger equation, and can be interpreted as a generalization of the Numerov process for the computational solution to the Schrödinger equation with quantum well structures. The proposed algorithm averages the probability slope’s discontinuity to converge the given energy to the nearest eigenstate, and generate complete eigenstates in a general heterojunction potential well. The new algorithm is applied to double-well III–V nanoscale MOSFET and generates each of the quantized levels.
    Journal of Computational Electronics 03/2008; 7(1):1-5. DOI:10.1007/s10825-007-0169-z · 1.37 Impact Factor
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    ABSTRACT: Metal contacts play an important role in nanowire devices and are expected to exhibit qualitatively different properties from those of planar contacts due to small contact cross sections. We numerically investigate certain unique properties of nanowire-metal contacts and demonstrate that contact resistivity increases as nanowire radius shrinks. This increase is more significant for nanowire-three-dimensional metal contacts than for nanowire-one-dimensional metal contacts. The underlying cause for this size effect is identified as the strong fringing field effects, which become more significant as temperature decreases. Our simulation provides a more complete understanding of the size effects on nanowire-metal contacts. (c) 2008 American Institute of Physics.
    Applied Physics Letters 02/2008; 92(8). DOI:10.1063/1.2889534 · 3.52 Impact Factor
  • L.M. Hillkirk, A.R. Hefner, R.W. Dutton
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    ABSTRACT: This paper presents a selection of results from numerical studies addressing various problems highly relevant to the operation of SiC power devices in power systems such as the speed optimization of high-voltage SiC PiN diodes and the operation of SiC thyristors under extremely- high-current pulse-power conditions. Various methods used to optimize the reverse-recovery performance of 4H-SiC PiN power diodes are studied, including base life time control, emitter efficiency reduction, and regional lifetime control. Pulse-power thyristors are also simulated to determine the limits of reliable performance due to self-heating-induced failure.
    Semiconductor Device Research Symposium, 2007 International; 01/2008
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    Cosmin Iorga, Yi-Chang Lu, R.W. Dutton
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    ABSTRACT: In system-on-chip applications, the digital switching noise propagates through substrate and power distribution to analog circuits, degrading their performance. To monitor and analyze the digital switching noise coupling, small and compact sensors that can be embedded within high-density circuits are essential. This paper presents PMOS-based differential substrate and power-supply sensors and an on-chip waveform sampler, which focus on wide bandwidth, reduced parasitic interactions, and small compact size. The bandwidth of the proposed sensors, which is implemented with an IBM 0.13- CMOS technology, is useful from DC to 1.6 GHz. Linearity is better than 1.5% for substrate and 6% for power-supply sensors. Power-supply rejection of 64 dB has been achieved in the substrate probing. The substrate noise coupling into the power-supply probing was below detectable limits. Experimentally reconstructed waveforms with 20-ps time resolution allowed the measurement of amplitude, rise time, and overshoot of transition edges.
    IEEE Transactions on Instrumentation and Measurement 01/2008; 56(6-56):2330 - 2337. DOI:10.1109/TIM.2007.908603 · 1.71 Impact Factor
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    Jongchol Kim, Chia-Yu Chen, Robert W. Dutton
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    ABSTRACT: A simple technique that can be implemented in the Monte Carlo (MC) simulation of transport in a quantum well is reported. The main difference between the proposed technique and existing methods is the use of three dimension momentum (3Dk) particles in the simulation of a quantum region. The use of 3Dk particles within a quantum well structure facilitates the MC simulation of transport in nanoscale devices which contain both the classical and quantum regions.
    11/2007: pages 77-80;
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    ABSTRACT: This article deals with performance of 3D-IC which is influenced by thermal effects as well as 3D packaging and parasitic effects. Actual circuit performance is difficult to predict as thermal and 3D packaging effects act in opposite ways. To provide design insight, a stacked wafer 3D-SOI technology was characterized and a thermal model was developed. Electro-thermal simulations of 3D-ICs were performed, and simulation results match measured data. Device noise is measured for this technology.
    SOI Conference, 2007 IEEE International; 11/2007
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    ABSTRACT: An Ultra-fast Transmission Line Pulsing (UFTLP) system is demonstrated. Very short pulses down to 40 ps with a large voltage range (up to 100 V in this work) can be generated. Gate oxide reliability is quantified in the 100 ps regime for the first time. Hard and soft breakdown transitions are clearly captured, and the results explain why some logic cells still function after breakdown events.
    29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD; 10/2007
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    ABSTRACT: The special issue consists of 25 papers, five of which are invited and 20 of which are contributed, that discuss topics such as process modeling, device modeling, and atomistic modeling, and address issues like reliability, manufacturability, and variability. The papers are briefly summarized here.
    IEEE Transactions on Electron Devices 10/2007; 54(9-54):2072 - 2078. DOI:10.1109/TED.2007.905342 · 2.36 Impact Factor
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    ABSTRACT: Accurate modeling of memory effects is important for design of amplifiers with high requirements on linearity. In this work, asymmetries in third order intermodulation distortion products (IM3) were measured for different tone-spacings and compared to simulations. An accurate large-signal model and careful modeling of the test circuit, especially the drain bias feeds is important for correct prediction of sideband asymmetries. Transient thermal measurements were employed to extract a thermal network with two time constants, one for the die and another one for the package. The IM3 asymmetries were found to be dominated by impedances in the output circuit for large tone-spacings; for very small tone-spacings (< 10 kHz), thermal effects have an important influence. The IM3 asymmetries agreed qualitatively well between simulations and measurements as a function of output power for different tone-spacings.
    Microwave Symposium, 2007. IEEE/MTT-S International; 07/2007
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    ABSTRACT: The present work is focussed on the trade off between conventional RF ESD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design. A narrow and a broadband RF test circuit were developed to put the benchmark on a firm basis. RF and ESD experiments are discussed, showing where the higher effort for the codesign approach starts to pay off.
    Microelectronics Reliability 07/2007; 47:1008-1015. DOI:10.1016/j.microrel.2006.11.007 · 1.21 Impact Factor
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    Reza Navid, Thomas H. Lee, R.W. Dutton
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    ABSTRACT: Experimental verification of noise models is one of the major challenges in noise modeling. A circuit-based noise characterization technique is introduced which uses phase noise measurement data to extract MOSFET noise parameters. After a brief discussion on MOSFET noise, experimental data is presented on the severity of excess noise in a 0.18mum CMOS process using the proposed technique. It is shown that in this process, the noise power of minimum-channel-length devices is up to 6 dB larger than that of long-channel devices. The proposed technique can be used for model verification as well as for parameter extraction in developing CMOS processes.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
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    ABSTRACT: The noise characteristics of today's short-channel devices are shown to have a better resemblance to ballistic devices than to long-channel metal oxide semiconductor field effect transistors MOSFETs. Therefore the noise characteristics of these devices are best modeled using a ballistic-MOSFET-based noise model. Extensive hydrodynamic device simulations are presented in support of this hypothesis and a simple compact model is introduced. This model is used for predicting the noise behavior of future nanoscale devices. Most of the findings of this work can also be applied to carbon nanotubes and nanowires because of their similarities to MOSFETs. © 2007 American Institute of Physics.
    Journal of Applied Physics 06/2007; 101(12). DOI:10.1063/1.2740345 · 2.19 Impact Factor
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    ABSTRACT: A post-breakdown transistor macro-model for 90nm and 130nm technologies is presented and experimentally verified. Oxide breakdown does not necessarily imply function failure. The location of breakdown within the circuit is also important. A simulation methodology implementing this macro-model is presented. This tool can be used to predict function failure for three different system-on-chip (SoC) design examples. Simulations agree well with failure analysis (FA) observations, verifying the validity of the macro-model
    Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007

Publication Stats

5k Citations
430.86 Total Impact Points


  • 1977–2014
    • Stanford University
      • • Department of Electrical Engineering
      • • Center for Integrated Systems
      Palo Alto, California, United States
  • 2009
    • University of Vienna
      • Faculty of Mathematics
      Vienna, Vienna, Austria
  • 2008
    • University of Texas at Austin
      Austin, Texas, United States
  • 2002–2008
    • Advanced Micro Devices
      Sunnyvale, California, United States
  • 2007
    • University of California, Santa Cruz
      Santa Cruz, California, United States
    • Rambus
      Sunnyvale, California, United States
  • 2005
    • Infineon Technologies
      München, Bavaria, Germany
  • 2004
    • Technische Universität Braunschweig
      Brunswyck, Lower Saxony, Germany
  • 2003
    • University of California, Santa Barbara
      • Department of Electrical and Computer Engineering
      Santa Barbara, California, United States
  • 2001
    • Mission College
      Santa Clara, California, United States
  • 1997
    • Hewlett-Packard
      Palo Alto, California, United States
  • 1994
    • Seoul National University
      • Department of Electrical and Computer Engineering
      Seoul, Seoul, South Korea
  • 1992
    • Lafayette College
      Easton, Pennsylvania, United States
  • 1990–1992
    • University of California, Berkeley
      Berkeley, California, United States