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ABSTRACT: It has been reported (Kuang et al., 1997; Lu et al., 1997) that
SOI passgate circuits suffer history effects and adverse initial-cycle
parasitic bipolar currents, which cause difficulties in circuit timing
and limit direct design reuse from original bulk circuits. SOI device
body history can also induce transfer characteristics mismatch in
dual-railed static or dynamic CMOS circuits, resulting in speed
degradation or functional failures. This paper describes an efficient
technique to alleviate initial-cycle bipolar currents while retaining
the low-V<sub>t</sub> floating body feature when the SOI devices
concerned are on. We also present a dynamic body discharge technique to
eliminate the mismatch problems in cross-coupled SOI CMOS topologies,
for use in a variety of circuit families such as cascade voltage switch
logic, latch-type sense amplifiers and analog operational amplifiers
SOI Conference, 1999. Proceedings. 1999 IEEE International; 02/1999
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[show abstract]
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ABSTRACT: Rapid fluctuations of power supply values, or switching noise, can
have a significant effect on VLSI circuit speed. This is shown by
comparing circuit simulations with measurements of the critical path
delay of a self-resetting SRAM. It is shown that including the measured
high frequency noise in the circuit simulation leads to very accurate
prediction of circuit speed
Electronics Letters 10/1997; · 0.96 Impact Factor
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W. Reohr,
J. Navarro,
Y.H. Chan,
Y. Chan,
M. Mayo,
B. Curran,
B. Krumm,
A. Pelella, P.F. Lu,
U. Bakhru,
S. Kowalczyk,
J. Rawlins,
S. Carey,
P. Wu
VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on; 07/1997
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VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on; 07/1997
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VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on; 07/1997
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ABSTRACT: This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for
Low Power Electronics and Design, 1996., International Symposium on; 09/1996
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ABSTRACT: A nonquasi-static (NQS) model accounting for intrinsic carrier
propagation delays in both B/E and B/C junctions is implemented in the
ASTAP circuit simulator to evaluate the impact of non-quasi-static
effects in saturated bipolar circuits. It is shown that while the extra
delay introduced by the NQS effects during the turn-on transition is
primarily due to the normal mode B/E NQS delay time, the more severe NQS
delay in the turnoff transition is caused mainly by the removal of the
saturation overdrive charges and the longer inverse mode B/C NQS delay
time
IEEE Transactions on Electron Devices 07/1994; · 2.32 Impact Factor
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ABSTRACT: As lithographic ground rules are scaled into the deep sub-micron regime in today's VLSI technologies, the proximity of different materials in a given device structure often induces significant mechanical stress. In this paper, we report the observation of the collector current (Ic) variation induced by the isolation trench in advanced bipolar devices. It is shown that as the trench-intrinsic device separation is pushed into deep sub-micron regime, Ic decreases in the npn transistors, while it increases in the pnp transistors. We attribute the latter to an in-plane biaxial tensile stress which lowers the electron mobiity while enhances the hole mobility in the 〈001〉 (vertical) crystal orientation.
Solid-State Electronics. 04/1994; 37(11):1871-1875.
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[show abstract]
[hide abstract]
ABSTRACT: Presents an ECL circuit with a Darlington configured dynamic
current source and active-pull-down emitter-follower stage for low-power
high-speed gate array application. The dynamic current source provides a
large dynamic current during the switching transient to improve the
power delay of the logic stage (current switch). A novel self-biasing
scheme for the dynamic current source and the active-pull-down
transistor with no additional devices and power in the biasing circuit
is described. Based on a 0.8-μm double-poly self-aligned bipolar
technology at a power consumption of 1 mW/gate, the circuit offers 28%
improvement in the loaded (FI/FO=3, C<sub>L</sub>=0.3 pF) delay and 42%
improvement in the load driving capability compared with the
conventional ECL circuit. The design and scaling considerations of the
circuit are discussed
IEEE Journal of Solid-State Circuits 01/1994; · 3.23 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: The effects of impact ionization are studied in the framework of a
standard hydrodynamic model. Three prescriptions of impact ionization
are implemented in the device simulator HFIELDS. They are: (1) a model
of Scholl and Quade developed from the Boltzmann transport equation; (2)
an empirical model of Baccarani and Stork; and (3) a postprocessor
method. Three thin-base Si bipolar devices are simulated. The numerical
results show that over a certain range of electric field, the
multiplication factors simulated from the Scholl-Quade model, and the
Baccarani-Stork model agree very well with the experiment. At very high
fields, these models tend to underestimate the net generation rate.
Invoking the postprocessor technique, good agreement is found between
simulation and experiment. However, at high fields the postprocessor
method can lead to erroneous base and collector currents. The
limitations of the Scholl-Quade model and how it can be extended for
high-field applications are considered
IEEE Transactions on Electron Devices 09/1993; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: An experimental 1-k×16 ECL (emitter coupled logic) dual-port
cache RAM block that has a read/write port and an independently
accessible read-only port is presented. Multiples of this block can be
used to construct a high-performance, large-capacity cache memory. This
dual-port memory cell is constructed by adding a differential
emitter-coupled sense circuit for the read-only port to the p-n-p-load
(or SCR-type) bipolar read/write single-port cell. The p-n-p-load cell
is chosen because of its smaller area and better soft-error immunity
than other types of bipolar memory cells. The cache block is fabricated
using a 0.8-μm, trench-isolated, double-poly, self-aligned 3.6-V
Si-bipolar technology with double metal layers and a W
local-interconnection layer
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International; 03/1993
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[show abstract]
[hide abstract]
ABSTRACT: A non-quasi-static (NQS) model accounting for intrinsic carrier propagation delays in both B/E and B/C junctions is implemented in the ASTAP circuit simulator to evaluate the impact of non-quasi-static effects in saturated bipolar circuits. It is shown that while the extra delay introduced by the NQS effects during the turn-on transition is primarily due to the normal mode B/E NQS time constant, the more severe NQS delay in the turn-off transition is caused mainly by the removal of the saturation over-drive charges and the longer inverse mode B/C NQS time constant.
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on; 02/1993
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[hide abstract]
ABSTRACT: It is shown that in the shallow junction formation for
high-performance p-n-p devices, the perimeter E-B junction may be
positioned inside the polysilicon due to insufficient boron dopants,
causing excessive low-level base leakage current and current gain
degradation. The I - V characteristic has an exp( qV
/2 kT ) dependence consistent with carrier recombination at
grain boundaries. Although the problem can be cured by using a deep
emitter drive-in, the resulting AC performance will be traded off due to
increased emitter charge storage. The nonuniform lateral profile limits
the minimum achievable emitter junction depth for useful p-n-p devices,
which in turn makes thin-base formation more difficult
IEEE Transactions on Electron Devices 01/1993; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: The design of an ECL circuit with AC-coupled self-biased dynamic
current source and active-pull-down emitter-follower stage for low-power
high-speed gate array applications is presented. The circuit features an
AC-coupled dynamic current source to improve the power-delay of the
logic stage (current switch). A self-biasing scheme for the dynamic
current source and the active-pull-down transistor with no additional
devices and power in the biasing circuit is described. Based on a
0.8-μm double-poly, self-aligned bipolar technology at a power
consumption of 1.0 mW/gate, the circuit offers 1.62× (1.90×)
improvement in the speed (load driving capability) of a loaded gate
compared with the conventional ECL circuit
IEEE Journal of Solid-State Circuits 09/1992; · 3.23 Impact Factor
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ABSTRACT: A detailed study on the effect of reverse base current (RBC) on
the switching behavior of bipolar BiCMOS circuits utilizing advanced
high-performance bipolar transistors is presented. It is shown that as
the collector doping N <sub>c</sub> is increased to overcome the
Kirk effect (base stretching) during the switching transient, the
avalanche-generated reverse base current in the collector-base junction
may cause problems for bipolar output devices switching out of
saturation. A basic bipolar inverter and various BiCMOS driver circuits
were simulated based on measured avalanche multiplication factors from
advanced bipolar transistors with various collector doping N
<sub>c</sub>. In the case of the basic bipolar inverter, the reverse
base current may prevent the switching device from being shut off
completely during the on-to-off transition and a self-sustained state
may result which reduces the output voltage swing. For the
common-emitter (CE) BiCMOS driver, a similar self-sustained state may
also occur with the added adverse effect of excessive leakage in
standby. Design and scaling considerations are discussed
IEEE Transactions on Electron Devices 09/1992; · 2.32 Impact Factor
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Custom Integrated Circuits Conference, 1992., Proceedings of the IEEE 1992; 06/1992
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[show abstract]
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ABSTRACT: The device design and performance of double-poly self-aligned
p-n-p technology, featuring a low-resistivity p<sup>+</sup>
subcollector, thin p-epi, and boron-doped poly-emitter are described.
Device isolation is provided by deep and shallow trenches which reduce
the collector-to-substrate capacitance while maintaining a high
breakdown voltage (⩾40 V). By utilizing a shallow emitter process in
conjunction with an optimized arsenic-base implant, devices with
emitter-base junction depths as shallow as 20 nm and base widths of less
than 100 nm were obtained. Cutoff frequencies of up to 27 GHz were
obtained, and the AC performance was demonstrated by an NTL-gate delay
of 36 ps and an active-pull-down (APD) ECL-gate delay of 20 ps. This
high-performance p-n-p technology was developed to be compatible with
existing double-poly n-p-n technologies. The matching speed of p-n-p
devices opens up new opportunities for high-performance complementary
bipolar circuits
IEEE Transactions on Electron Devices 07/1991; · 2.32 Impact Factor
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J.Y.-C. Sun,
J.H. Comfort,
J. Warnock,
J.D. Cressler,
G. Patton,
J.M.C. Stork,
J. Burghartz,
D. Harame,
E. Crabbe, P.-F. Lu,
M. Arienzo,
B. Meyerson
[show abstract]
[hide abstract]
ABSTRACT: The advent of low temperature epitaxy processes provides a new
degree of freedom for bipolar device scaling. This paper describes new
vertical scaling concepts and process technology elements required for
advanced scaled bipolar (NPN and PNP) devices which will be the core of
high-performance application-specific bipolar, BiCMOS, or complementary
bipolar/BiCMOS logic and memory chips. In particular, the authors
address key issues such as transit time reduction by SiGe base band-gap
engineering, junction field/capacitance control by using lightly-doped
emitter (LDE) and collector (LDC) concepts, lateral scaling (reduction
of parasitic R and C) by advanced self-aligned structures and trench
isolations, and liquid-nitrogen temperature (LNT) operation. Challenges
for future BiCMOS and complementary bipolar/BiCMOS process technologies
are examined
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on; 06/1991
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[show abstract]
[hide abstract]
ABSTRACT: An active pull-down output stage that utilizes a composite
junction FET (JFET), applied in a high-speed low-power emitter-coupled
logic (ECL) circuit, is described. The composite JFET structure is
produced by modifying the existing bipolar transistor layout so that a
p-channel JFET is formed next to an n-p-n transistor without need of any
extra process steps. This p-channel JFET is a four-terminal device: the
intrinsic base region defines the channel, the two separate extrinsic
bases become the source and drain, the emitter region is the primary
gate, and the collector is used as the back gate. The JFET has the same
doping profile as the n-p-n bipolar transistor in the intrinsic device
region. Simulation results based on a 0.8-μm double poly-Si,
self-aligned bipolar technology indicate that the circuit with a typical
loading at a power consumption of 1 mW per gate offers a 24% improvement
in the pull-down delay and a 53% improvement in the load driving
capability compared with the conventional ECL circuit
IEEE Journal of Solid-State Circuits 05/1991; · 3.23 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: The authors report how self-aligned pnp devices with basewidths
close to 50 nm have been fabricated using a preamorphizing Ge implant
prior to the As base implant. They investigated the sensitivity of pnp
performance to collector epi thickness, base width and the energy of the
base implant, culminating in the achievement of devices with f
<sub>T</sub> as high as 38 GHz. ECL (emitter coupled logic) ring
oscillators built with these pnp devices have delays as small as 35 ps
per stage, demonstrating that the device parasitics have been
successfully minimized. Both the f <sub>T</sub> of 38 GHz and
the 35 ps ECL delay represent new records for pnp devices, showing a
performance level comparable to that of current high-performance npn
technologies
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International; 01/1991
