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ABSTRACT: In this paper, classical adder architectures applied to Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, a hybrid solution is proposed such that the optimal trade-off between architectures and technology is reached. The resulting scheme yields optimized performance after the use of Xilinx place and route tools.
04/2006: pages 462-471;
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ABSTRACT: This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated.
01/2002;
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ABSTRACT: The paper presents a FPGA technology snapshot. It shows the status
of the latest reprogrammable FPGA families and discusses the
capabilities of FPGA design tools. The accent is on comparison of FPGA
capacities, advanced architectural features, partitioning for synthesis,
floorplanning, macro block processing, memory implementation techniques,
etc
Rapid System Prototyping, 2000. RSP 2000. Proceedings. 11th International Workshop on; 02/2000
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ABSTRACT: This paper discusses the FPGA partitioning strategies for open
rapid prototyping boards and proprietary prototyping systems, where the
constraints of a low number of utilized devices and high performance are
critical. Partitioning should handle large designs and produce efficient
solutions. The paper first presents the advanced partitioning strategies
and then considers a case study example of 1 million gates. The required
partitioning solution was obtained by combining the described manual and
automatic partitioning and pin multiplexing techniques
Rapid System Prototyping, 1999. IEEE International Workshop on; 08/1999
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ABSTRACT: This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed by Kuznar et al. (1995), but instead of using the replication and re-optimization, it takes force of the classical iterative improvement partitioning techniques. The basic effort consists in guiding the classical algorithms in their solution space exploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solution and carefully tuning the basic parameters of the classical algorithms such as definition of size constraints for feasible moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results comparable to the best published results, and even outperforms them for the largest benchmarks
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings; 02/1999
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ABSTRACT: The paper presents a strategy for high-speed prototyping on FPGAs.
The traditional “glue” synthesis strategy may not be
sufficient for obtaining FPGA prototypes working at real speed. A key
possibility to accelerate the performance of FPGA designs is the
utilisation of the architectural features of modern FPGAs. To do this,
no “push-button” solutions exists. The way to do this is to
process one by one the critical blocks of the design and to decide about
the implementation strategy for each block. As an example, a case study
of a microprocessor circuit is presented. The microprocessor should be
able to work in real time at 10 MHz frequency. To reach this speed in
the Altera FLEX 10 KA technology, a special implementation strategy was
elaborated for the microprocessor's RAM and ALU blocks
Rapid System Prototyping, 1998. Proceedings. 1998 Ninth International Workshop on; 07/1998
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ABSTRACT: In this paper, classical adder and multiplier architectures
applied to the Xilinx XC5200 FPGA are compared. To inherit advantages of
both structural and algorithmic approaches, hybrid solutions are
proposed such that the optimal trade-off between architectures and
technology is reached. The resulting schemes yield optimized performance
after the use of Xilinx place and route tools
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on; 02/1998
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Design Automation Conference, 1997. Proceedings of the 34th; 07/1997
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ABSTRACT: Many users of ASIC technologies are switching to ASIC prototyping on FPGAs for lower cost functional verification which is also a reprogrammable implementation that allows the user to make quick design changes for faster development time. This paper presents a new ASIC prototyping process that provides for large ASIC migration to LUT-based netlists (e.g., XILINX/4000 or ALTERA/FLEX) and routing support for reprogrammable interconnect between FPGAs (e.g., APTIX FPICs or ICUBE FPIDs). Comparisons with MCNC and industrial benchmarks show improvements over XILINX NEOCAD and ALTERA MAXPLUSII mapping and partitioning tools
Rapid System Prototyping, 1996. Proceedings., Seventh IEEE International Workshop on; 07/1996
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ABSTRACT: The work presented in this paper aims at defining the best
solution for designing defect-tolerant scan chains, taking into account
the sensitivity of the yield improvement on various parameters. The
results presented demonstrate that a noticeable yield increase can be
achieved, but only if the selected redundant architecture is coherent
with the implementation details, in particular the multiplexer
electrical structure. It is also shown that the most straightforward
approach, i.e., the triple modular redundancy, can be very inefficient
if optimized majority gates are not available for the implementation
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,; 12/1995
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ABSTRACT: Today, there is an increasing need for fault tolerance capabilities in integrated circuits used in critical applications such as aircraft control. The classical way to achieve fault tolerance in a logic block is to triplicate it and to implement a majority voting block on the outputs (Triple Modular Redundancy, or TMR). The Single Independent Decoder (SID) architecture was defined in order to achieve with a lower hardware overhead the tolerance of faults in the circuit control part (the Finite State Machine), and more precisely in the sequencing logic (next-state logic and state register). A dedicated synthesis tool (ASYL-SdF) has been developed and the results obtained on a large set of examples in terms of silicon area and dependability evaluation have shown its efficiency, especially compared with the TMR implementation of the sequencing logic (TMR Seq)
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.; 04/1995
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[show abstract]
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ABSTRACT: This paper summarizes a practical experiment in designing a defect
tolerant microprocessor and presents the underlying principles. Unlike
memory integrated circuits, microprocessors have an irregular structure
which complicates both the task of incorporating redundancy for defect
tolerance in the design and the task of analyzing the resulting yield
increase. The main goal of this paper is to present the detailed yield
analysis of a defect tolerant microprocessor with an irregular structure
which has been successfully fabricated. The approaches employed for
achieving the goal of yield enhancement in the data path and the control
part of the microprocessor are described first. Then, the yield
enhancement due to the incorporated redundancy is analyzed. Finally,
some practical and theoretical conclusions are drawn
IEEE Transactions on Computers 01/1995; · 1.10 Impact Factor
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ABSTRACT: This paper addresses the detection of permanent or transient
faults in complex VLSI circuits, with a particular focus on faults
leading to sequencing errors. On-line test devices are automatically
generated by a specific synthesis tool (ASYL-SdF), avoiding design time
overhead. Two approaches based on control-flow checking methods are
available to the designer and it is shown that each of these approaches
leads, in some cases, to the cheapest implementation. In particular,
noticeable gains can be obtained compared with the classical approach
based on duplication
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on; 11/1994
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ABSTRACT: In this paper, a new package partitioning tool from Innovative Synthesis Technologies is described that uses functional cone partitioning [ICCAD93] to find high size to I/O ratio partitions. Partitioning for performance is provided by containing whole critical paths within packages, made easy with functional cone partitioning. Hierarchy is respected, allowing for partitioning into heterogeneous devices. As an extension of the ASYL+ netlist synthesis and technology migration system, the tool partitions for multiple PLD, FPGA, and ASIC technologies for desired market price and performance
Fast Prototyping of IC Designs, IEE Colloquium on; 07/1994
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ABSTRACT: Presents the design of a dedicated chip achieving the recognition
phase of layered neural networks. General back-propagation (GBP) and
learning vector quantization (LVQ) neurons can be emulated on this chip
(called the OCR-chip). It consists of five processors: four neuron
processors interconnected in a ring, each are computing several states
of different GBP neurons, and a LVQ processor used to compute the states
of the LVQ neurons. Connections between GBP neurons folded on the same
processor are implemented in each processor by using an address
generator based on modulus m counters. An optical character recognition
(OCR) neural network (840 neurons in 4 layers and 800 LVQ neurons) is
used as demonstrator
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.; 01/1994
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ABSTRACT: Circuit partitioning for packages that have limited numbers of IO
pins is a critical problem with FPGAs. Common FPGAs have prespecified
maximum gate count limits on the order of five to ten times the number
of usable IO pins. Traditional min-cut approaches lack the ability to
find such constrained partitions with high gate to IO pin ratios. In
this paper, a new partitioning algorithm is presented that uses cone
structures. Cone structures are minimum cut partitioning structures for
netlists with low fanout, and clustering structures for partitioning
netlists with high fanout. Cone structures also allow for full
containment of critical paths. When used with good Merging/Cutting
strategies, results show that the cone partitioning algorithms
introduced here produce better partitions than min-cut
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on; 12/1993
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ABSTRACT: Presents hardware and software techniques for configuring a wafer
scale 2D array. A switching network independent of the processing
elements (PEs) has been designed and implemented. Two algorithms find
and program an optimized target array in a reversible or irreversible
manner. This paper is based on a wafer scale design for low-level image
processing
IEEE Transactions on Components Hybrids and Manufacturing Technology 12/1993;
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ABSTRACT: This paper proposes a new type of expression for Boolean functions
called lexicographical expressions. The basic idea is to impose an input
ordering for factoring logical expressions. Several algebraic properties
are presented and relations with classical algebraic theory are
established. The main result is that all elementary factorizations
defined by (Cokernel, Kernel) pairs “compatible” with an
input order are all “algebraically compatible,” i.e., are
all parts of a single factorization of the function. Thus for a given
input order a unique factorization is defined. This leads to fast
division procedures. Basic techniques for obtaining lexicographical
factorizations are presented. First, a precedence matrix and an updating
procedure are defined and used later to select an input order and a
corresponding compatible factorization. Second, a factorization
technique respecting a fixed order is detailed. This method is then
applied to multilevel synthesis using standard cells which was the
original motivation of this work. The goal is to reduce wiring
complexity. A lexicographical factorization leads to a wiring area
reduction due to the structuring of the logic into layers in which the
inputs enter the layout in the order given by the factorization.
Experimental results comparing this approach to classical ones are
given. These results include routing ratio measurements, routing
structure observation, global area measurement and critical path
estimation. All these results are analyzed after place and route, using
an industrial tool (COMPASS Design Automation tool)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12/1993; · 1.27 Impact Factor
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ABSTRACT: Implementing single fault tolerant finite state machines (FSMs) in
VLSI circuits might be done using triplication and voting (TMR).
Alternatives are based on the use of an error correcting (SEC) code
during the state assignment. Such architectures are studied and their
characteristics are analyzed for a set of international and industrial
FSM benchmarks. The results demonstrate that one of these architectures
leads in some cases to implementation with less hardware overhead than
TMR and should actually be considered for some types of circuits
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on; 11/1993
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ABSTRACT: Signature analysis is often used in the test area to reduce the
amount of information to check. The drawback of this compaction is its
non-zero aliasing probability, i.e. the possibility to obtain a correct
signature in spite of errors in the compacted words. Up to now, the
studies on aliasing have focused on BIST applications and do not
consider correlations between errors in two compacted words. However,
online test methods also use signature analysis. The reported
experiments show that, in this context and for some types of faults, the
existing correlations have a noticeable impact on the aliasing
probability. Further theoretical studies taking into account these
correlations are therefore required to model the aliasing observed at
each compaction step. It also seems that checking a signature in the
middle of a linear block of instructions is better than checking it just
before or after a branching instruction
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on; 11/1993
