G. Saucier

Grenoble Institute of Technology, Grenoble, Rhône-Alpes, France

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Publications (101)12.74 Total impact

  • B. Laurent, G. Bosco, G. Saucier
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    ABSTRACT: In this paper, classical adder architectures applied to Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, a hybrid solution is proposed such that the optimal trade-off between architectures and technology is reached. The resulting scheme yields optimized performance after the use of Xilinx place and route tools.
    04/2006: pages 462-471;
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    ABSTRACT: This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated.
    01/2002;
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    H. Krupnova, G. Saucier
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    ABSTRACT: The paper presents a FPGA technology snapshot. It shows the status of the latest reprogrammable FPGA families and discusses the capabilities of FPGA design tools. The accent is on comparison of FPGA capacities, advanced architectural features, partitioning for synthesis, floorplanning, macro block processing, memory implementation techniques, etc
    Rapid System Prototyping, 2000. RSP 2000. Proceedings. 11th International Workshop on; 02/2000
  • Helena Krupnova, Gabriele Saucier
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    ABSTRACT: The given paper presents the state of the art in the FPGA-based logic emulation. The analysis of the existing emulation solutions is performed according to the following classification: (1) large emulation systems (Quickturn [26], Ikos [16], MentorGraphics [21]); (2) semi-custom rapid prototyping boards (Aptix [3], Simutech [24]); (3) custom prototyping solutions (Transmogrifier2 [20], Weaver [6], Replica [18], FPGA vendors demonstration and prototyping boards [31], [2], microprocessor-based boards, etc.). Each system is exposed in terms of its capacity, architecture, used FPGAs and performance.
    Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings; 01/2000
  • H. Krupnova, C. Rabedaoro, G. Saucier
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    ABSTRACT: This paper discusses the FPGA partitioning strategies for open rapid prototyping boards and proprietary prototyping systems, where the constraints of a low number of utilized devices and high performance are critical. Partitioning should handle large designs and produce efficient solutions. The paper first presents the advanced partitioning strategies and then considers a case study example of 1 million gates. The required partitioning solution was obtained by combining the described manual and automatic partitioning and pin multiplexing techniques
    Rapid System Prototyping, 1999. IEEE International Workshop on; 08/1999
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    H. Krupnova, G. Saucier
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    ABSTRACT: This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed by Kuznar et al. (1995), but instead of using the replication and re-optimization, it takes force of the classical iterative improvement partitioning techniques. The basic effort consists in guiding the classical algorithms in their solution space exploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solution and carefully tuning the basic parameters of the classical algorithms such as definition of size constraints for feasible moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results comparable to the best published results, and even outperforms them for the largest benchmarks
    Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings; 02/1999
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    Helena Krupnova, Gabriele Saucier
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    ABSTRACT: This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed in (12), but instead of using the replication and re-optimization, it takes force of the classical iterative improvement parti- tioning techniques ((4),(14)). The basic effort consists in guiding the classical algorithms in their solution space ex- ploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solu- tion and carefully tuning the basic parameters of classical algorithms such as definition of size constraints for feasi- ble moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results com- parable to the best published results ((12),(16)), and even outperforms them for biggest benchmarks.
    1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany; 01/1999
  • Helena Krupnova, Gabriele Saucier
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    ABSTRACT: The paper addresses the design partitioning into multiple FPGA devices. The industrial experience shows that the designers were never satisfied by the full automatic partitioning: as the design size grows, it takes longer CPU times and produces poor results. The present paper proposes an algorithm which may be integrated into the mixed interactive manual/automatic partitioning framework. The hierarchy nodes of the design are selected one by one and assigned to a defined set of FPGA devices. The automatic partitioning algorithm is called to split a big node among the selected subset of devices taking into account previous assignments to these devices. Experimental results show that the proposed approach works well for big industrial circuits.
    Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings; 01/1999
  • Helena Krupnova, Gabriele Saucier
    01/1999
  • D.R. Brasen, G. Saucier
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    ABSTRACT: Circuit designers and high-level synthesis tools have traditionally used circuit hierarchy to partition circuits into packages. However hierarchical partitioning can not be easily performed if hierarchical blocks have too large a size or too many I-Os. This problem becomes more frequent with field-programmable gate arrays (FPGAs) which commonly have small size limits and up to ten times smaller I-O pin limits. An I-O bottleneck often occurs which during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. More critical timing paths between packages are cut and circuit operational frequencies are drastically reduced. In this paper, two new partitioning algorithms are presented that use cone structures to partition large hierarchical blocks into FPGA's. Cone structures are minimum cut partitioning structures for netlists with low fanout, and clustering structures for partitioning netlists with high fanout. Cone structures also allow for full containment of critical paths. When used with good merging and cutting strategies, results show the cone partitioning algorithms given here produces fewer FPGG partitions than min-cut with good performance
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 08/1998; · 1.09 Impact Factor
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    ABSTRACT: The paper presents a strategy for high-speed prototyping on FPGAs. The traditional “glue” synthesis strategy may not be sufficient for obtaining FPGA prototypes working at real speed. A key possibility to accelerate the performance of FPGA designs is the utilisation of the architectural features of modern FPGAs. To do this, no “push-button” solutions exists. The way to do this is to process one by one the critical blocks of the design and to decide about the implementation strategy for each block. As an example, a case study of a microprocessor circuit is presented. The microprocessor should be able to work in real time at 10 MHz frequency. To reach this speed in the Altera FLEX 10 KA technology, a special implementation strategy was elaborated for the microprocessor's RAM and ALU blocks
    Rapid System Prototyping, 1998. Proceedings. 1998 Ninth International Workshop on; 07/1998
  • B. Laurent, G. Bosco, G. Saucier
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    ABSTRACT: In this paper, classical adder and multiplier architectures applied to the Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, hybrid solutions are proposed such that the optimal trade-off between architectures and technology is reached. The resulting schemes yield optimized performance after the use of Xilinx place and route tools
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on; 02/1998
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    ABSTRACT: The goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. The circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. The floorplanning is then guided b y this cone structuring and has two innov ativ e features:first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, th us a significant reduction is obtained; second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.
    Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays; 01/1998
  • Helena Krupnova, B. Behnam, Gabriele Saucier
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    ABSTRACT: In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance ...
    Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays; 01/1998
  • Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier
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    ABSTRACT: This paper presents a knowledge-based system for ASIC prototyping on FPGAs. ASIC prototyping is known to be a difficult task. The rapid increase of densities and speeds of FPGAs, as well as sophisticated architectural features require changes in prototyping methodologies. FPGA prototypes should often work at real speeds. Obtaining efficient implementations demands reach design experience and perfect knowledge of the FPGA technology. The interest is in accumulating knowledges and reusing parts of previous designs. The idea was to facilitate prototyping by creating the knowledge-based system which stores the designer skills in form of technology-dependent design rules and reuse blocks.
    Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings; 01/1998
  • Bernard Laurent, G. Bosco, Gabriele Saucier
    Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings; 01/1997
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    Helena Krupnova, Ali Abbara, Gabriele Saucier
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    ABSTRACT: Not Available
    Design Automation Conference, 1997. Proceedings of the 34th; 01/1997
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    H. Krupnova, C. Rabedaoro, G. Saucier
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    ABSTRACT: Because the VLSI circuits complexity growth, the trend in design is towards divide-and-conquer schemes, in which circuits are composed of blocks, standard macros or custom macros. From the other side, to allow an implementation of large digital circuits, increased capacity target FPGAs are organized hierarchically. In this paper, we present a hierarchical FPGA floorplanning method which takes into account both the hierarchy of the design and the hierarchy of the target. The method aims at minimization the timing and balancing cost of the floorplan and is based on automatic detection of macro blocks and assigning them to the target FPGA hierarchical zones.
    01/1997;
  • D. Brasen, G. Saucier
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    ABSTRACT: Many users of ASIC technologies are switching to ASIC prototyping on FPGAs for lower cost functional verification which is also a reprogrammable implementation that allows the user to make quick design changes for faster development time. This paper presents a new ASIC prototyping process that provides for large ASIC migration to LUT-based netlists (e.g., XILINX/4000 or ALTERA/FLEX) and routing support for reprogrammable interconnect between FPGAs (e.g., APTIX FPICs or ICUBE FPIDs). Comparisons with MCNC and industrial benchmarks show improvements over XILINX NEOCAD and ALTERA MAXPLUSII mapping and partitioning tools
    Rapid System Prototyping, 1996. Proceedings., Seventh IEEE International Workshop on; 07/1996
  • P. Brahic, R. Leveugle, G. Saucier
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    ABSTRACT: The work presented in this paper aims at defining the best solution for designing defect-tolerant scan chains, taking into account the sensitivity of the yield improvement on various parameters. The results presented demonstrate that a noticeable yield increase can be achieved, but only if the selected redundant architecture is coherent with the implementation details, in particular the multiplexer electrical structure. It is also shown that the most straightforward approach, i.e., the triple modular redundancy, can be very inefficient if optimized majority gates are not available for the implementation
    Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,; 12/1995

Publication Stats

689 Citations
12.74 Total Impact Points

Institutions

  • 1990–2006
    • Grenoble Institute of Technology
      Grenoble, Rhône-Alpes, France
  • 1998
    • Cadence Design Systems, Inc.
      San Jose, California, United States
  • 1994
    • Insight Publishers Ltd
      Bristol, England, United Kingdom
  • 1988
    • British Telecom
      Londinium, England, United Kingdom