Katsuhiro Tomioka

Hokkaido University, Sapporo, Hokkaidō, Japan

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Publications (48)191.95 Total impact

  • Katsuhiro Tomioka, Takashi Fukui
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    ABSTRACT: We report on a fabrication of tunnel field-effect transistors using InGaAs nanowire/Si heterojunctions and the characterization of scaling of channel lengths. The devices consisted of single InGaAs nanowires with a diameter of 30 nm grown on p-type Si(111) substrates. The switch demonstrated steep subthreshold-slope (30 mV/decade) at drain-source voltage (VDS) of 0.10 V. Also, pinch-off behavior appeared at moderately low VDS, below 0.10 V. Reducing the channel length of the transistors attained a steep subthreshold slope (<60 mV/decade) and enhanced the drain current, which was 100 higher than that of the longer channels.
    Applied Physics Letters 01/2014; 104(7):073507-073507-4. · 3.79 Impact Factor
  • Katsuhiro Tomioka, Masatoshi Yoshimura, Takashi Fukui
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    ABSTRACT: We report on changes of turn-on voltage in InAs-Si heterojunction steep subthreshold-slope transistor by Zn-pulsed doping technique for InAs nanowire-channel. The doping of the nanowire-channel moderately changes turn-on voltage from negative to positive voltage, with keeping a steep subthreshold-slope of 30 mV/decade under reverse bias direction. Formation of pseudo-intrinsic InAs segment is found to be important to make normally-off transistor with steep subthreshold-slope.
    Nano Letters 11/2013; · 13.03 Impact Factor
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    ABSTRACT: We report surface-passivated core--shell InP nanowire array solar cells fabricated using catalyst-free selective-area metal organic vapor phase epitaxy. Reflectance measurements confirm enhanced light absorption due to significantly reduced reflectance over a wide spectral range. The wide-band-gap outer shell layer of core-multishell nanowires effectively passivates the large surface area of the nanowires, increasing the short-circuit current density and elevating the energy conversion efficiency by 6.35% under AM1.5G illumination. This passivation technique could open a new approach to nanowire-based photovoltaics with higher energy efficiency.
    Applied Physics Express 05/2013; 6(5):2301-. · 2.73 Impact Factor
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    ABSTRACT: Semiconductor nanowires (NWs) are good candidate for light-absorbing material in next generation photovoltaic and III--V NW-based multi-heterojunction solar cells using lattice-mismatched material system are expected as high energy-conversion efficiencies under concentrated light. Here we demonstrate core--shell GaAs NW arrays by using catalyst-free selective-area metal organic vapor phase epitaxy (SA-MOVPE) as a basis for multijunction solar cells. The reflectance of the NW array without any anti-reflection coating showed much lower reflection than that of a planar wafer. Next we then fabricated core--shell GaAs NW array solar cells with radial p--n junction. Despite the low reflectance, the energy-conversion efficiency was 0.71% since a high surface recombination rate of photo-generated carriers and poor ohmic contact between the GaAs and transparent indium--tin-oxide (ITO) electrode. To avoid these degradations, we introduced an InGaP layer and a Ti/ITO electrode. As a result, we obtained a short-circuit current of 12.7 mA cm-2, an open-circuit voltage of 0.5 V, and a fill factor of 0.65 for an overall efficiency of 4.01%.
    Japanese Journal of Applied Physics 05/2013; 52(5):5002-. · 1.07 Impact Factor
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    ABSTRACT: The growth mechanism of GaAs nanowires (NWs) grown on polycrystalline silicon (poly-Si) thin films using selective-area metalorganic vapor-phase epitaxy was investigated. Wire structures were selectively grown in the mask openings on a poly-Si substrate. The appearance ratio of wire structures strongly depended on the growth conditions and deposition temperature of the poly-Si substrate. Evaluation of the grown shapes and growth characteristics revealed that GaAs NWs grown on a poly-Si substrate have the same growth mechanism as conventional GaAs NWs grown on a single-crystalline GaAs or Si substrate. Experiments showed that the wire structure yield can be improved by increasing the Si grain size and/or increasing the Si deposition temperature. The growth model proposed for understanding NW growth on poly-Si is based on the mask opening size, the Si grain size, and the growth conditions. The ability to control the growth mode is promising for the formation of NWs with complex structures on poly-Si thin layers.
    Nanotechnology 03/2013; 24(11):115304. · 3.84 Impact Factor
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    ABSTRACT: Heterojunction solar cells were formed with a position-controlled InP nanowire array sputtered with indium tin oxide (ITO). The ITO not only acted as a transparent electrode but also as forming a photovoltaic junction. The devices exhibited an open-circuit voltage of 0.436 V, short-circuit current of 24.8 mA/cm2, and fill factor of 0.682, giving a power conversion efficiency of 7.37% under AM1.5 G illumination. The internal quantum efficiency of the device was higher than that of the world-record InP cell in the short wavelength range.
    Applied Physics Letters 01/2013; 103(24):243111-243111-3. · 3.79 Impact Factor
  • Katsuhiro Tomioka, Takashi Fukui
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    ABSTRACT: Main target in future LSI is to achieve low power consumption while enhancing performance. There are many concerns to lower the power consumption in recent CMOS technologies, such as multi-gate architecture for suppressing short-channel effect and OFF-state leakage current. The state-of-the-art FET offered by the gate structure surely reduces the power dissipation, but the power-scaling will be limited by FET in itself since the reduction in supply voltage in Si-based MOSFETs has some difficulties, such as low carrier mobility under lower electrical field and physically limited subthreshold slope (SS). Especially, utilization of steep subthreshold-slope transistor such as tunnel FETs (TFETs) and impact ionization FETs is important for the low power circuits because physical limitation due to carrier thermal diffusion stops a scaling of the power consumption even if the multi-gate structure and III-Vs are utilized. Thus, another channel materials and transport mechanisms should be addressed mutually in CMOS technologies, and these distinct features should possess good compatibility with the Si-based CMOS. In this regard, heterojunctions formed across the III-V nanowire (NW) and Si would be promising building blocks for the future extended CMOS technologies. Here, we present integration of III-V nanowires on Si by selective-area growth and concept for steep SS transistor using III-V nanowire/Si heterojunctions.
    Energy Efficient Electronic Systems (E3S), 2013 Third Berkeley Symposium on; 01/2013
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    ABSTRACT: We present a bidirectional growth mode of InP nanowires grown by selective-area metalorganic vapor-phase epitaxy (SA-MOVPE). We studied the effect of the supply ratio of DEZn ([DEZn]) on InP grown structure morphology and crystal structures during the SA-MOVPE. Two growth regimes were observed in the investigated range of the [DEZn] on an InP(111)B substrate. At low [DEZn], grown structures formed tripod structures featuring three nanowires branched toward the [111]A directions. At high [DEZn], we obtained hexagonal pillar-type structures vertically grown on the (111)B substrate. These results show that the growth direction changes from [111]A to [111]B as [DEZn] is increased. We propose a growth mechanism based on the correlation between the incident facet of rotational twins and the shapes of the grown structures. Our results bring us one step closer to controlling the direction of nanowires on a Si substrate that has a nonpolar nature. They can also be applied to the development of InP nanowire devices.
    Nano Letters 08/2012; 12(9):4770-4. · 13.03 Impact Factor
  • Katsuhiro Tomioka, Masatoshi Yoshimura, Takashi Fukui
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    ABSTRACT: Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.
    Nature 08/2012; 488(7410):189-92. · 38.60 Impact Factor
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    ABSTRACT: We investigate the vibrational modes of a triangular array of anisotropic, hexagonal GaAs nanopillars on a GaAs substrate through ultrafast changes in optical reflectivity. By comparison with simulations, we identify GHz resonances, mode shapes, and damping. In addition, by varying the pillar diameter, height, and pitch, we distinguish collective and localized modes. A proper understanding of substrate-attached nanostructure dynamics will lead to better characterization of nanosensors based on perturbations to vibrational resonances.
    Applied Physics Letters 03/2012; 100(13). · 3.79 Impact Factor
  • Source
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    ABSTRACT: We have investigated the optical properties of a single InAsP quantum dot embedded in a standing InP nanowire. Elongation of the transverse exciton-spin relaxation time of the exciton state with decreasing excitation power was observed by first-order photon correlation measurements. This behavior is well explained by the motional narrowing mechanism induced by Gaussian fluctuations of environmental charges in the nanowire. The longitudinal exciton-spin relaxation time is evaluated by the degree of the random polarization of emission originating from exciton states confined in a single-nanowire quantum dot by using Mueller calculus based on Stokes parameters representation. The reduction in the random polarization component with decreasing excitation power is caused by suppression of the exchange interaction of electron and hole due to an optically induced internal electric field by the dipoles at the wurtzite and zinc-blende heterointerfaces in the InP nanowire.
    Physical review. B, Condensed matter 02/2012; 85(7). · 3.77 Impact Factor
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    ABSTRACT: We fabricated nanowire light-emitting diodes (LEDs) using InP nanowires (NWs). Indium phosphide NWs with axial p--n junction were grown by selective-area metalorganic vapor phase epitaxy. The results of secondary-electron-microscopy (SEM) observation and photoluminescence measurement showed the formation of wurtzite InP NWs with some mixture of zincblende crystal phase, as expected from the used growth conditions. NW-LEDs were fabricated by sputtering indium tin oxide (ITO) after a planarization process for the top contact and AuZn evaporation for the backside contact. Current--voltage characterisitics showed clear rectifying characteristics with a small leakage current, and fairly linear current--light output characteristics were observed. By designing the pitch of the NW array, emission from individual NWs was confirmed, which opens the possibility for realizing a single NW-LED applicable to single-photon emitters.
    Japanese Journal of Applied Physics 02/2012; 51(2). · 1.07 Impact Factor
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    ABSTRACT: The fabrication of GaAs- and InP-based III-V semiconductor nanowires with axial/radial heterostructures by using selective-area metal-organic vapor-phase epitaxy is reviewed. Nanowires, with a diameter of 50–300 nm and with a length of up to 10 μm, have been grown along the 〈111〉B or 〈111〉A crystallographic orientation from lithography-defined SiO2 mask openings on a group III-V semiconductor substrate surface. An InGaAs quantum well (QW) in GaAs/InGaAs nanowires and a GaAs QW in GaAs/AlGaAs or GaAs/GaAsP nanowires have been fabricated for the axial heterostructures to investigate photoluminescence spectra from QWs with various thicknesses. Transmission electron microscopy combined with energy dispersive X-ray spectroscopy measurements have been used to analyze the crystal structure and the atomic composition profile for the nanowires. GaAs/AlGaAs, InP/InAs/InP, and GaAs/GaAsP core-shell structures have been found to be effective for the radial heterostructures to increase photoluminescence intensity and have enabled laser emissions from a single GaAs/GaAsP nanowire waveguide. The results have indicated that the core-shell structure is indispensable for surface passivation and practical use of nanowire optoelectronics devices.
    Journal of Nanotechnology 01/2012; 2012.
  • Source
    Journal of Crystal Growth 01/2012; · 1.55 Impact Factor
  • Katsuhiro Tomioka, M. Yoshimura, Takashi Fukui
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    ABSTRACT: In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterojunction TFET with surrounding-gate architecture and high-k dielectrics. Control of resistances in this device structure is important for achieving steep-slope switching. A minimum subthreshold slope (SS) of the TFET is 21 mV/dec at VDS of 0.10 - 1.00 V.
    VLSI Technology (VLSIT), 2012 Symposium on; 01/2012
  • Katsuhiro Tomioka, Takashi Fukui
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    ABSTRACT: The III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We review position-controlled growth of III-V NWs on Si substrate by selective-area growth and discuss how to control growth directions of III-V NW on Si. Finally, we demonstrate the integrations of III-V NW-based light-emitting diodes (LEDs) array on Si. These demonstrations should have broad applications in laser diodes and photodiodes with functionality not enabled by conventional NW.
    Semiconductor Nanostructures for Optoelectronic Devices: Processing, Characterization and Applications, NanoScience and Technology. 01/2012;
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    ABSTRACT: We demonstrate position-controlled III-V semiconductor nanowires (NWs) by using selective-area metal-organic vapor phase epitaxy and their application to solar cells. Efficiency of 4.23% is achieved for InP core-shell NW solar cells. We form a 'flexible NW array' without a substrate, which has the advantage of saving natural resources over conventional thin film photovoltaic devices. Four junction NW solar cells with over 50% efficiency are proposed and discussed.
    AMBIO A Journal of the Human Environment 01/2012; 41 Suppl 2:119-24. · 2.30 Impact Factor
  • Nano Letters 12/2011; · 13.03 Impact Factor
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    ABSTRACT: We review the position-controlled growth of III-V nanowires (NWs) by selective-area metal-organic vapor-phase epitaxy (SA-MOVPE). This epitaxial technique enables the positioning of the vertical NWs on (111) oriented surfaces with lithographic techniques. Core-shell structures have also been achieved by controlling the growth mode during SA-MOVPE. The core-shell III-V NW-based devices such as light-emitting diodes, photovoltaic cells, and vertical surrounding-gate transistors are discussed in this article. Nanometer-scale growth also enabled the integration of III-V NWs on Si regardless of lattice mismatches. These demonstrated achievements should have broad applications in laser diodes, photodiodes, and high-electron mobility transistors with functionality on Si not made possible with conventional Si-CMOS techniques.
    Journal of Materials Research. 09/2011; 26(17):2127 - 2141.
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    ABSTRACT: Indium phosphide (InP) nanowires, which have crystal phase mixing and transition from zinc blende (ZB) to wurtzite (WZ), are grown in intermediate growth conditions between ZB and WZ by using selective-area metalorganic vapor phase epitaxy (SA-MOVPE). The shape of InP nanowires is tapered unlike ZB or WZ nanowires. A growth model has been developed for the tapered nanowires, which is simply described as the relationship between tapered angle and the ratio of ZB and WZ segments. In addition, the peak energy shift in photoluminescence measurement was attributed to the quantum confinement effect of the quantum well of the ZB region located in the polytypic structure of ZB and WZ in nanowires.
    Nano Letters 09/2011; 11(10):4314-8. · 13.03 Impact Factor

Publication Stats

388 Citations
191.95 Total Impact Points

Institutions

  • 2006–2014
    • Hokkaido University
      • • Graduate School of Information Science and Technology
      • • Department of Electronics and Information Engineering
      Sapporo, Hokkaidō, Japan
  • 2011
    • Japan Science and Technology Agency (JST)
      Edo, Tōkyō, Japan