Katsuhiro Tomioka

Hokkaido University, Sapporo, Hokkaidō, Japan

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Publications (62)220.93 Total impact

  • Katsuhiro Tomioka · Fumiya Ishizaka · Takashi Fukui ·
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    ABSTRACT: III-V compound semiconductor and Ge are promising channel materials for future low-power and high-performance integrated circuits. A heterogeneous integration of these materials on same platform, however, raises serious problem due to huge mismatch of carrier mobility. We proposed direct integration of perfectly vertical-aligned InAs nanowires on Ge as a way of new alternative integrated circuits, and demonstrated high-performance InAs nanowire-vertical surrounding-gate transistor. Virtually 100% yield of vertical-aligned InAs nanowires were achieved by controlling initial surface of Ge and high quality InAs nanowires were obtained regardless of lattice mismatch (6.7%). The transistor performance showed significant higher conductivity with good gate control as compared to Si-based conventional field-effect transistors: drain current was 0.65 mA/μm and transconductance was 2.2 mS/μm at drain-source voltage of 0.50 V. These demonstrations are a first step for building alternative integrated circuits using vertical III-V/multi-gate planar Ge FETs.
    Nano Letters 10/2015; DOI:10.1021/acs.nanolett.5b02165 · 13.59 Impact Factor
  • K. Tomioka · J. Motohisa · T. Fukui ·
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    ABSTRACT: MOSFETs using III-V channels with multi-gate architecture and tunnel junctions are promising alternative building blocks for highperformance and low power nanoelectronic circuits. CMOS. In this paper, we review recent advances in direct integration of vertical III-V nanowire (NW)-channel on Si and FET application such as vertical III-V NW surrounding-gate transistors (SGTs) and tunneling FET (TFETs) using III-V NW/Si heterojunctions.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 06/2015; 2015. DOI:10.1109/VLSI-TSA.2015.7117561
  • Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: This chapter summarizes the growth of semiconductor nanocrystals, including quantum well, wire, nanowire, and quantum dot with selective-area growth. The position-controlled growth of nanocrystals by using faceting growth and mechanisms is described. In addition, microchannel epitaxy is outlined as one of the types of selective-area epitaxy.
    Handbook of Crystal Growth, 01/2015: pages 749-793; , ISBN: 9780444563699
  • Eiji Nakai · Muyi Chen · Masatoshi Yoshimura · Katsuhiro Tomioka · Takashi Fukui ·

    Japanese Journal of Applied Physics 01/2015; 54(1):015201. DOI:10.7567/JJAP.54.015201 · 1.13 Impact Factor
  • Muyi Chen · Eiji Nakai · Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: III-V compound semiconductor nanowire (NW) arrays have exhibited remarkable behavior in photovoltaic applications. We embedded an orderly vertical InP NW array in poly(dimethylsiloxane) (PDMS) and peeled it off from the substrate to form a AuZn contact. The sample with the substrate exhibited a very high average absorptance of 92%. However, when the array was peeled off, the optical absorptance degraded, particularly in the longer-wavelength region. After the AuZn was deposited on the back side of the NW array, the absorptance increased. This technology could enable a new approach for NW-based photovoltaics with a lower fabrication cost. (C) 2015 The Japan Society of Applied Physics
    Applied Physics Express 01/2015; 8(1). DOI:10.7567/APEX.8.012301 · 2.37 Impact Factor
  • Fumiya Ishizaka · Yoshihiro Hiraya · Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: A GaP nanowire is promising from the viewpoint of device applications because when its crystal phase is changed from zinc blende (ZB) to wurtzite (WZ), its band gap changes from indirect to direct. GaP in the WZ phase is theoretically and experimentally shown to have the possibility of “green” emission. Here we report on the growth of WZ GaP in InP/GaP core–shell nanowires by selective-area metal–organic vapor-phase epitaxy (SA-MOVPE). WZ InP nanowires were used as a template for transferring the WZ structure to GaP. Transmission electron microscopy revealed that WZ GaP was grown on the sidewalls of the InP core in the lateral 〈−2 1 1〉 direction and that ZB GaP was grown on the top of the InP core in the axial 〈1 1 1〉A direction. A growth model for the different crystal structures of the GaP shell is proposed from the viewpoint of the growth direction. The WZ structure is “transferred” from the InP core to the GaP shell only when GaP grows in the direction perpendicular to the WZ stacking direction of the InP core. This so-called “crystal structure transfer” can also be applied to p- and n-doped GaP and is therefore promising for fabricating WZ-GaP-based light-emitting diodes.
    Journal of Crystal Growth 11/2014; 411. DOI:10.1016/j.jcrysgro.2014.10.024 · 1.70 Impact Factor
  • Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: We report on the recent progress in electronic applications using III?V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III?V NWs on Si under specific growth conditions. Detailed studies of the III?V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III?V/Si heterojunction. The vertical III?V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III?V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III?V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.
    Journal of Physics D Applied Physics 09/2014; 47(39):394001. DOI:10.1088/0022-3727/47/39/394001 · 2.72 Impact Factor
  • Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: We report on vertical tunnel field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions. III-V nanowire (NW) was heterogeneously integrated on Si by selective-area growth with precise positioning. The III-V NW/Si heterojunction consisting of a few misfit dislocations shows a large Zener tunnel current under positive bias and band-to-band tunneling current under forward bias. The vertical TFET using InGaAs NW/Si heterojunction, which is vertical surrounding-gate architecture, demonstrated a steep turn-on behavior and very low parasitic leakage current.
    ECS Transactions 05/2014; 61(3):81-89. DOI:10.1149/06103.0081ecst
  • Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: We report on a fabrication of tunnel field-effect transistors using InGaAs nanowire/Si heterojunctions and the characterization of scaling of channel lengths. The devices consisted of single InGaAs nanowires with a diameter of 30 nm grown on p-type Si(111) substrates. The switch demonstrated steep subthreshold-slope (30 mV/decade) at drain-source voltage (VDS) of 0.10 V. Also, pinch-off behavior appeared at moderately low VDS, below 0.10 V. Reducing the channel length of the transistors attained a steep subthreshold slope (<60 mV/decade) and enhanced the drain current, which was 100 higher than that of the longer channels.
    Applied Physics Letters 02/2014; 104(7):073507-073507-4. DOI:10.1063/1.4865921 · 3.30 Impact Factor
  • Masatoshi Yoshimura · Eiji Nakai · Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: Heterojunction solar cells were formed with a position-controlled InP nanowire array sputtered with indium tin oxide (ITO). The ITO not only acted as a transparent electrode but also as forming a photovoltaic junction. The devices exhibited an open-circuit voltage of 0.436 V, short-circuit current of 24.8 mA/cm2, and fill factor of 0.682, giving a power conversion efficiency of 7.37% under AM1.5 G illumination. The internal quantum efficiency of the device was higher than that of the world-record InP cell in the short wavelength range.
    Applied Physics Letters 12/2013; 103(24):243111-243111-3. DOI:10.1063/1.4847355 · 3.30 Impact Factor
  • Katsuhiro Tomioka · Masatoshi Yoshimura · Eiji Nakai · Fumiya Ishizaka · Takashi Fukui ·
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    ABSTRACT: In this paper, we present recent progress in the integration of vertical III-V nanowire-channels on Si by selective-area epitaxy and demonstrations of high-performance III-V vertical surrounding-gate transistors with high-k dielectrics with an EOT of less than 1 nm, modulation doping technique, and challenges in steep subthreshold-slope switching using III-V nanowire/Si heterojunctions as building blocks for low power circuits.
    2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
  • Katsuhiro Tomioka · Masatoshi Yoshimura · Takashi Fukui ·
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    ABSTRACT: We report on changes of turn-on voltage in InAs-Si heterojunction steep subthreshold-slope transistor by Zn-pulsed doping technique for InAs nanowire-channel. The doping of the nanowire-channel moderately changes turn-on voltage from negative to positive voltage, with keeping a steep subthreshold-slope of 30 mV/decade under reverse bias direction. Formation of pseudo-intrinsic InAs segment is found to be important to make normally-off transistor with steep subthreshold-slope.
    Nano Letters 11/2013; 13(12). DOI:10.1021/nl402447h · 13.59 Impact Factor
  • Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: We report on the recent achievement of III-V nanowire applications for a vertical FET and steep subthreshold-slope transistors on Si. III-V nanowires (NWs) were heterogeneously integrated on Si by selective-area metal-organic vapor-phase epitaxy with precise positioning on Si(111) surfaces. Nanometer-scale growth enabled the integration of III-V NWs on Si regardless of apparent lattice mismatches. A non-planar vertical transistor architecture, which is a vertical surrounding-gate structure, was demonstrated on Si substrate. This demonstration should have broad applications for use in high-electron mobility transistors and tunnel FETs with functionality that is not possible with conventional Si-CMOS technologies.
    224th ECS Meeting; 10/2013
  • Takashi Fukui · Masatoshi Yoshimura · Eiji Nakai · Katsuhiro Tomioka ·
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    ABSTRACT: Core-multi-shell InP/AlInP nanowire-array solar cells were fabricated using selective-area metal-organic vapor phase epitaxy. The wider-bandgap outer shell layer passivates InP nanowires effectively, increasing conversion efficiency to 6.35%.
    CLEO: Science and Innovations; 06/2013
  • Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: Non-planar III-V MOSFETs are promising candidate transistor for future n-MOSFET with low power and high speed. Recently, bottom-up In0.7Ga0.3As nanowire-channels on Si have been reported. However, the report was limited to large-sized nanowire-channels and EOT is much thicker than the practical devices. In this presentation, we advances the device fabrication by using completely gate-first process and investigate the EOT scaling from 0.70 nm to 2.75 nm. Furthermore, we investigate diameter-scaling of InGaAs/InAlAs/InP core-multishell nanowire-HEMT structure with thin EOT.
    2013 71st Annual Device Research Conference (DRC); 06/2013
  • Source
    Masatoshi Yoshimura · Eiji Nakai · Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: We report surface-passivated core--shell InP nanowire array solar cells fabricated using catalyst-free selective-area metal organic vapor phase epitaxy. Reflectance measurements confirm enhanced light absorption due to significantly reduced reflectance over a wide spectral range. The wide-band-gap outer shell layer of core-multishell nanowires effectively passivates the large surface area of the nanowires, increasing the short-circuit current density and elevating the energy conversion efficiency by 6.35% under AM1.5G illumination. This passivation technique could open a new approach to nanowire-based photovoltaics with higher energy efficiency.
    Applied Physics Express 05/2013; 6(5):2301-. DOI:10.7567/APEX.6.052301 · 2.37 Impact Factor
  • Eiji Nakai · Masatoshi Yoshimura · Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: Semiconductor nanowires (NWs) are good candidate for light-absorbing material in next generation photovoltaic and III--V NW-based multi-heterojunction solar cells using lattice-mismatched material system are expected as high energy-conversion efficiencies under concentrated light. Here we demonstrate core--shell GaAs NW arrays by using catalyst-free selective-area metal organic vapor phase epitaxy (SA-MOVPE) as a basis for multijunction solar cells. The reflectance of the NW array without any anti-reflection coating showed much lower reflection than that of a planar wafer. Next we then fabricated core--shell GaAs NW array solar cells with radial p--n junction. Despite the low reflectance, the energy-conversion efficiency was 0.71% since a high surface recombination rate of photo-generated carriers and poor ohmic contact between the GaAs and transparent indium--tin-oxide (ITO) electrode. To avoid these degradations, we introduced an InGaP layer and a Ti/ITO electrode. As a result, we obtained a short-circuit current of 12.7 mA cm-2, an open-circuit voltage of 0.5 V, and a fill factor of 0.65 for an overall efficiency of 4.01%.
    Japanese Journal of Applied Physics 05/2013; 52(5):5002-. DOI:10.7567/JJAP.52.055002 · 1.13 Impact Factor
  • Fumiya Ishizaka · Keitaro Ikejiri · Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: We studied the growth of indium-rich InGaP nanowires (NWs) on InP (111)A substrates by selective-area metal organic vapor phase epitaxy (SA-MOVPE). We obtained vertically aligned InGaP NWs by optimizing growth conditions, such as group III supply ratio and V/III ratio. We found that the height, diameter, shape, and composition of InGaP NWs depended significantly on the supply ratios of trimethylgallium (TMGa) and trimethylindium (TMIn). As the supply ratio of TMGa was increased, the lateral growth was drastically enhanced, and the uniformity of NWs deteriorated. Furthermore, the sidewall facets of NWs changed from {(2) over bar 11} to {(1) over bar 10} as the supply ratio of TMGa was increased, indicating the possibility of structural transition from wurtzite (WZ) to zinc blende (ZB). We propose a possible growth model for such lateral growth, uniformity, and structural transition. Photoluminescence (PL) measurements revealed that the Ga compositions ranged approximately from 0 to 15%. Our results show that highly uniform InGaP NWs can be grown by controlling the growth conditions. (C) 2013 The Japan Society of Applied Physics
    Japanese Journal of Applied Physics 04/2013; 52(4S):04CH05. DOI:10.7567/JJAP.52.04CH05 · 1.13 Impact Factor
  • Keitaro Ikejiri · Fumiya Ishizaka · Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: The growth mechanism of GaAs nanowires (NWs) grown on polycrystalline silicon (poly-Si) thin films using selective-area metalorganic vapor-phase epitaxy was investigated. Wire structures were selectively grown in the mask openings on a poly-Si substrate. The appearance ratio of wire structures strongly depended on the growth conditions and deposition temperature of the poly-Si substrate. Evaluation of the grown shapes and growth characteristics revealed that GaAs NWs grown on a poly-Si substrate have the same growth mechanism as conventional GaAs NWs grown on a single-crystalline GaAs or Si substrate. Experiments showed that the wire structure yield can be improved by increasing the Si grain size and/or increasing the Si deposition temperature. The growth model proposed for understanding NW growth on poly-Si is based on the mask opening size, the Si grain size, and the growth conditions. The ability to control the growth mode is promising for the formation of NWs with complex structures on poly-Si thin layers.
    Nanotechnology 03/2013; 24(11):115304. DOI:10.1088/0957-4484/24/11/115304 · 3.82 Impact Factor
  • Katsuhiro Tomioka · Takashi Fukui ·
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    ABSTRACT: Main target in future LSI is to achieve low power consumption while enhancing performance. There are many concerns to lower the power consumption in recent CMOS technologies, such as multi-gate architecture for suppressing short-channel effect and OFF-state leakage current. The state-of-the-art FET offered by the gate structure surely reduces the power dissipation, but the power-scaling will be limited by FET in itself since the reduction in supply voltage in Si-based MOSFETs has some difficulties, such as low carrier mobility under lower electrical field and physically limited subthreshold slope (SS). Especially, utilization of steep subthreshold-slope transistor such as tunnel FETs (TFETs) and impact ionization FETs is important for the low power circuits because physical limitation due to carrier thermal diffusion stops a scaling of the power consumption even if the multi-gate structure and III-Vs are utilized. Thus, another channel materials and transport mechanisms should be addressed mutually in CMOS technologies, and these distinct features should possess good compatibility with the Si-based CMOS. In this regard, heterojunctions formed across the III-V nanowire (NW) and Si would be promising building blocks for the future extended CMOS technologies. Here, we present integration of III-V nanowires on Si by selective-area growth and concept for steep SS transistor using III-V nanowire/Si heterojunctions.
    Energy Efficient Electronic Systems (E3S), 2013 Third Berkeley Symposium on; 01/2013

Publication Stats

1k Citations
220.93 Total Impact Points


  • 2006-2014
    • Hokkaido University
      • • Research Center for Integrated Quantum Electronics
      • • Graduate School of Information Science and Technology
      Sapporo, Hokkaidō, Japan
  • 2010-2013
    • Japan Science and Technology Agency (JST)
      Edo, Tōkyō, Japan