S. Deleonibus

Cea Leti, Grenoble, Rhône-Alpes, France

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Publications (248)156.89 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.
    Junction Technology (IWJT), 2013 13th International Workshop on; 01/2013
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    ABSTRACT: In this paper we propose the optimization of the programming operation scheme of Silicon nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power applications. Using the program kinetic characteristics and a dynamic current measurement method, the programming window and the energy consumption during Channel Hot Electrons programming are deeply analyzed; evaluating ramp and box pulse with various gate and drain voltage biases. Finally the critical role of the tunnel oxide is evaluated to satisfy both retention and consumption requirements.
    2012 International Semiconductor Conference Dresden-Grenoble; 09/2012
  • S. Deleonibus
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    ABSTRACT: Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress and reduced variability. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will be introduced to make it possible.
    Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on; 01/2012
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    ABSTRACT: 3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.
    International Electron Devices Meeting (IEDM); 12/2011
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    ABSTRACT: Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials (Ge, diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.
    International Journal of High Speed Electronics and Systems 11/2011; 16(01).
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    ABSTRACT: In this paper, an extensive investigation of hybrid molecular/Si field-effect memories is presented, where redox ferrocene (Fc) molecules play the role of the memory charge storage nodes. Engineering of the organic linkers between Fc and Si is achieved by grafting Fc with different linker lengths. The study shows a clear correlation between results from atomistic computational density functional theory, electrochemical measurements (cyclic voltammetry) and electrical data obtained by a detailed study on capacitors and pseudo-MOS devices. Physical-chemical analyses (atomic force microscopy, high-resolution transmission electron microscopy, and X-ray photoelectron spectroscopy), corroborate the quality of molecular layers on devices.
    IEEE Transactions on Nanotechnology 04/2011; · 1.80 Impact Factor
  • Simon Deleonibus
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    ABSTRACT: The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.
    Sciece China. Information Sciences 01/2011; 54:990-1003. · 0.71 Impact Factor
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    ABSTRACT: After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650 °C). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.
    Microelectronic Engineering 01/2011; 88(4):331-335. · 1.22 Impact Factor
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    ABSTRACT: 3D monolithic integration, thanks to its high vertical density of interconnections, is the only available option for applications requiring connections at the transistor scale. However to achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low thermal budget top FET still have to be solved. In this work, a 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given. Significant breakthroughs have been obtained using a full wafer molecular bonding with thin interlayer dielectric and an original salicidation process stabilized up to 650°C enabling to reach high performance for the top and bottom transistor. With such technology, we demonstrate functional top and bottom transistors as well as 3D structures such as invertors and SRAMs.
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
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    ABSTRACT: For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4¿ of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20 nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22 nm nodes. We demonstrate pFET devices with promising electrical behavior (I<sub>ON</sub> = 790 ¿A/¿m; I<sub>OFF</sub> = 60 nA/¿m @ V<sub>DS</sub> = -1.2 V; L<sub>g</sub> = 30 nm), suitable for high performance applications. Excellent SCE control is also reported down to 30 nm (DIBL = 50 mV/V), through the use of Double Gate transistors.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: In this paper, Silicon on Diamond (SOD) substrates were fabricated using the direct bonding process in two different technologies: the BESOI (Bonded and Etched-back SOI) and the Smart-Cut™ process. The polycrystalline diamond (C∗) film deposited by Chemical Vapor Deposition assisted by Microwave Plasma (MPCVD) was planarized by an innovative process which induces a significant decrease of the diamond surface roughness (1.2 nm for the 200 nm diamond layer). The planarization method as well as the entire SOD substrate process by the BESOI or the Smart-Cut™ technology are described in the paper. Cross sectional high-resolution transmission microscopy reveals the good quality of the future silicon channel on top of the thin diamond layer.
    Solid-State Electronics 01/2010; 54(2):158-163. · 1.48 Impact Factor
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    ABSTRACT: Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. We have proven this planar option to be easier to integrate than the non planar devices like FinFET. This paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, within wafer variability and scalability are addressed through silicon data (down to 18nm gate length) and TCAD analyses. Solutions to the Multiple VT challenges and non logic devices (ESD, I/Os) are also reported.
    Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2010
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    ABSTRACT: In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline diamond layers (C*) can be integrated as a buried oxide layer offering new opportunities in terms of thermal management.We describe different technological process flow investigations leading to SOD by bonding C* layer in the stack. As starting material we used poly-crystalline thin diamond films in the 200nm to 7000nm range of thickness. The C* is deposited by Chemical Vapour Deposition assisted by Microwave Plasma (MPCVD) onto various 50mm wafers such as Si, SOI and polycrystalline silicon carbide (pSiC). As the roughness of the diamond layer is not directly compatible with a wafer bonding integration, an innovative smoothening process in 3 steps has been developed and named “DPE” for Deposition, Planarization and Etching. Using the DPE process, the roughness of 5µm thick diamond layer could be reduced from 50 to 3nm RMS and down to 1.5nm RMS for a thin 200nm layer.In order to demonstrate the feasibility of a GaN on SOD micro-structure design for HEMT applications, layer transfers have been carried out by a bonding and thinning process from C*/Si bulk using oxide bonding layers. From thermal spreading efficiency consideration, new processes of fabrication of SOD/poly-SiC substrate are in progress involving BESOI or Si Smart Cut™ technologies and poly-Si bonding layer starting from C*/poly-SiC.Pure SOD substrate were also fabricated by using C*/SOI and poly-Si bonding layer in a BESOI technology. A thin active silicon layer (70nm) of 50mm diameter onto a 140nm thick diamond BOX layer has been transferred on 200mm diameter Si substrate for future MOSFET's devices demonstrations. Significant progress has been done in diamond layer integration by wafer bonding.
    Diamond and Related Materials 01/2010; 19(7):796-805. · 1.71 Impact Factor
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    ABSTRACT: We have fabricated Silicon-On-Diamond (SOD) substrates on which, for the first time, we integrated n and p Fully Depleted MOSFETs high-K/metal gate down to 200 nm gate length. The devices show excellent electrical characteristics and a 57% improvement of the thermal resistance compared to the co-processed one on standard SOI.
    SOI Conference, 2009 IEEE International; 11/2009
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    ABSTRACT: In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.
    IEEE Electron Device Letters 08/2009; · 2.79 Impact Factor
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    ABSTRACT: In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect control down to L<sub>G</sub> = 50 nm. Both gains in density and performance have been studied with advanced design rules. Processing CMOS on each layer leads to an average 40% density improvement as compared to 2D standard layout.
    VLSI Technology, 2009 Symposium on; 07/2009
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    ABSTRACT: Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO<sub>2</sub> gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO<sub>2</sub> and N<sup>+</sup>poly-Si/SiO<sub>2</sub> gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high- kappa/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D silicide position.
    IEEE Transactions on Electron Devices 07/2009; · 2.06 Impact Factor
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    ABSTRACT: Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow I<sub>OFF</sub> (16 pA/mum) and high I<sub>ON</sub> (N: 2.27 mA/mum and P: 1.32 mA/mum) currents are obtained on silicon on insulator (SOI) with a high-kappa/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-kappa/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher V<sub>Dsat</sub> for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.
    IEEE Transactions on Electron Devices 07/2009; · 2.06 Impact Factor
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    ABSTRACT: Due to a new quasi-ballistic extraction methodology dedicated to low-longitudinal-field conditions, experimental carrier mean-free-paths have been determined on strained and unstrained fully depleted silicon-on-insulator (n-FDSOI) devices with Si film thickness ranging from 11.8 to 2.5 nm, gate length down to 30 nm, and a TiN/HfO<sub>2</sub> gate stack. Electron mobility evolution with the Si film thickness, reported in a previous study, is explored and quantitatively explained. Moreover, through inversion charge and temperature deep investigations, dominant carrier transport mechanisms are analyzed. It is experimentally revealed that transport degradation occurs in short and thin channels, which is shown to be mainly due to additional Coulomb scatterings rather than ballistic artifact in both strained and unstrained devices.
    IEEE Transactions on Nanotechnology 04/2009; · 1.80 Impact Factor

Publication Stats

1k Citations
156.89 Total Impact Points

Institutions

  • 1999–2013
    • Cea Leti
      Grenoble, Rhône-Alpes, France
    • Eawag: Das Wasserforschungs-Institut des ETH-Bereichs
      Duebendorf, Zurich, Switzerland
  • 2008–2009
    • STMicroelectronics
      Genève, Geneva, Switzerland
  • 2006
    • Soitec
      Rhône-Alpes, France
  • 2002–2006
    • French National Centre for Scientific Research
      Lutetia Parisorum, Île-de-France, France
  • 2004
    • University of Padova
      • Department of Information Engineering
      Padova, Veneto, Italy