[Show abstract][Hide abstract] ABSTRACT: a b s t r a c t In this work double-gate pentacene TFT architecture is proposed and experimentally investigated. The devices are fabricated on a polyimide substrate based on a process that combines three levels of stencil lithography with standard photolithography. Similarly to the operation of a conventional double-gate sil-icon FET, the top-gate bias modulates the threshold voltage of the bottom-gate transistor and signifi-cantly improves the transistor sub-threshold swing and leakage current. Moreover, the double gate TFT shows good promise for the enhancement of I ON /I OFF , especially by the control of I OFF in devices with poor top interfaces.
[Show abstract][Hide abstract] ABSTRACT: In this poster, the methodologies to make GAA strained Si nanowire MOSFETs (local oxidation) and 3D stack of Si nanowire MOSFETs, all on bulk Si, are addressed in details.
[Show abstract][Hide abstract] ABSTRACT: In this work a double-gate pentacene TFT architecture is presented. The devices are fabricated on a polyimide substrate using three aligned levels of stencil lithography along with standard photolithography, which enable a soft yet well-controlled device processing. The positive impact of the top gate voltage control on reducing the leakage current and significantly improving the subthreshold swing of the device is demonstrated. Moreover, this original design shows good promise for the enhancement of I<sub>ON</sub>/I<sub>OFF</sub> TFT characteristics.
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
[Show abstract][Hide abstract] ABSTRACT: In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.
IEEE Electron Device Letters 08/2009; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This work reports on gate voltage dependent source and drain series resistance and associated barrier height in modified Double Gate Schottky MOSFETs with dopant segregation. We show that in our devices the series resistances is significantly reduced by lowering the Schottky Barrier Height (SBH). The series resistance and the barrier have been extracted using an external series resistance method and Arrhenius plots, respectively. Series resistances as low as 400 Omega.mu m for V-G>V-T and SBH of 0.1eV at V-G=V-T, are reported Finally, this paper points our the correlation of R-T(V-G) and Phi(B)(V-G) in DG Schottky MOSFETs and the importance of the simultaneous extraction and modeling.
[Show abstract][Hide abstract] ABSTRACT: We have investigated the p- and n-type dopants in thin SGOI (20 nm) material obtained by Ge enrichment. The samples are doped with either BF2 or arsenic or phosphorus and then annealed with either a spike or a 15 s rapid thermal annealing in a temperature range of 850–1050 °C. We have observed that sheet resistance (Rsh) obtained in SGOI for p-type is approximately independent of annealing conditions. In addition, these values are lower than the SOI (20 nm) reference. Result reveals that almost all BF2 atoms remain in SGOI substrate giving rise to low Rsh, whereas dopant out diffuses and segregates in SOI. In contrast, Rsh measured with arsenic and phosphorus implanted SGOI samples is higher than SOI.