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ABSTRACT: IEEE Std 1500 enables automation and hence allows for easier and faster integration of embedded cores into an SoC. This article describes an automated test development system based on the concept of embedded test.
IEEE Design and Test of Computers 03/2009; · 1.39 Impact Factor
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ABSTRACT: The BurstModetrade test clocking methodology, first presented in, is improved to handle circuits with synchronous clocks of different frequencies. An on-chip clock controller allows to select a large number of clock waveforms necessary to test synchronous cross-domain paths at-speed and control supply voltage variations. The methodology is applicable to both ATPG and BIST and only requires combinational analysis tools. The methodology is applied to a large circuit to adjust power supply margins of an at-speed BIST test.
Test Conference, 2008. ITC 2008. IEEE International; 11/2008
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ABSTRACT: The use of group (or bit) write enable in memories is becoming very common in embedded memories. The circuitry used to achieve these functions need be thoroughly tested for different kind of defects using specific test sequence. However, most BIST algorithms assume that these write enables are forced active during the global write cycle in the BIST run. This paper presents a serial interface BIST algorithm that is used to test defect on bit/group write enables of these memories.
Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on; 09/2004
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ABSTRACT: Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed tests can be generated onchip. However, it is also necessary to test the DC and AC parameters of the input/output (I/O) circuitry. This paper describes how most I/O pin characteristics can be tested cost-effectively with a variety of novel techniques that exploit the 1149.1 and 1149.4 test standards. The techniques measure VOL/IOL, VOH/IOH, VIH, and VIL at DC, perform at-speed I/O wrap, and test on-chip power rail impedance, all via minimum pin-count (MPC) access. The 1149.4 bus is also suitable, of course, for testing mixed-signal functions. The paper then discusses costs and benefits of MPC testing of high pin-count ICs on a low cost tester to show that testing costs can be reduced to insignificance.
Test Conference, 2002. Proceedings. International; 02/2002
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ABSTRACT: A new embedded test technique which provides full at-speed testing
of board level interconnect is described. The proposed technique is
fully compatible with the IEEE 1149.1 boundary scan standard. The
technique extends the standard's architecture to provide for
synchronized at-speed timing control of the boundary scan cells so that
test data can be applied and captured across the interconnect at system
speeds
Test Conference, 1999. Proceedings. International; 02/1999
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ABSTRACT: Today's complex electronic products are harder to test using
traditional external methods. Built in self test can frequently be used
without significantly increasing a product's size, cost and production
time
Computer 12/1996; · 1.47 Impact Factor
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ABSTRACT: A new fault insertion method to help debug diagnostic software of
telecommunications systems is described. The method makes use of
boundary scan to inject multiple and un-correlated faults in a telecom
system carrying traffic. Both hardware and software implementation
aspects are discussed. The new method allows the use of structural test
as part of diagnostics software to locate faults
Test Conference, 1995. Proceedings., International; 11/1995
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ABSTRACT: Describes the architecture of a time-slot interchange (TSI) SRAM
for a SONET switching application and its associated BIST architecture.
To reduce the number of data RAMs required for full switching, the
memory throughput is boosted by providing multiplexed access to the core
at twice the system clock rate. The nature of the memory requires a
novel BIST architecture to ensure full test coverage and ensure easy
access of the BIST function at different levels of system integration
Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on; 09/1995
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ABSTRACT: This paper describes a 155 MHz wide-word cache design and its test
integration features. Design techniques for high speed CAM with single
ended match line sensing and highly integrated RAM are described. A new
cache BIST algorithm based on the SMARCH algorithm is presented. New
techniques are described for the insertion of cache BIST access points
into a high speed data path without compromising mission mode
performance. Performance results of cache memory used for
telecommunications microprocessor applications with 1 Kb of CAM
referencing a 5 Kb RAM are presented
Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on; 09/1994
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ABSTRACT: The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode
IEEE Design and Test of Computers 02/1994; 11(1):7-17. · 1.39 Impact Factor
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ABSTRACT: A family of modular memories with a built-in self-test interface
designed using a synchronous self-timed architecture is described. This
approach is ideally suited to modular memories embedded within
synchronous systems due to its simple boundary specification, excellent
speed/power performance, and ease of modelling. The basic port design is
self-contained and extensible to any number of ports sharing access to a
common-core cell array. The same design has been used to implement
modular one-, two-, and four-part SRAMs and a one-port DRAM based on a
four-transistor (4-T) cell. The latter provides a 45% core cell density
improvement over the one-port SRAM. Nominal access and cycle times of
5.5 ns for 64 kb blocks have been shown for a 0.8 μm BiCMOS process
with no memory process enhancements. System operation at 100 MHz has
been demonstrated on a broadband time-switch chip containing 96 kb of
two-port SRAM
IEEE Journal of Solid-State Circuits 04/1993; · 3.23 Impact Factor
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ABSTRACT: The issues of printed circuit board (PCB) interconnect testing are
addressed in the context of boundary-scan architecture. Boundary-scan
architecture is treated here as the framework for a PCB level built-in
self-test (BIST). A novel BIST method is developed which utilizes
various features of the architecture. Boundary-scan architecture is
shown to have the capability to generate time-efficient test vector
sets. Response compaction within the boundary-scan chain is introduced
to reduce shift out time as well as to simplify detection and diagnosis.
However, the proposed BIST schemes require some extensions of the
standard boundary-scan cells, and the schemes can work only if every
boundary-scan cell of every IC on the PCB has the proposed extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11/1992; · 1.27 Impact Factor
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Test Conference, 1992. Proceedings., International; 10/1992
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Custom Integrated Circuits Conference, 1992., Proceedings of the IEEE 1992; 06/1992
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ABSTRACT: Addresses the problem of efficiently testing scannable ASICs in a
board-level and system-level environment. The method makes use of a
serial testability bus (ETM or IEEE 1149.1) and takes advantage of the
presence of identical components on the boards. The main benefits of the
method are a significant reduction in test time and test data to be
stored. Results obtained for an actual system show a reduction in test
time of about 20 times for a module with 50 ASICs. The extra board area
required was less than 2% for all boards of the module
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on; 02/1991
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ABSTRACT: It is proposed that a pseudorandom sequence and a single weighted
random sequence be used to implement built-in self-test (BIST)
efficiently in a large integrated scan circuit which would otherwise
need an excessive pseudorandom test length. A method of determining the
weight set and the approximate pseudorandom and weighted random test
lengths, based on fast fault simulation tools, is suggested. By
modifying specific scan cells, the BIST hardware conditionally generates
the weighted stream locally, at specific input sites. A weighted control
signal is used to regulate the proportion of weighted and pseudorandom
inputs. Apart from determining that, in the cases examined, one weight
set was sufficient for a notable decrease in test time, it was also
noticed that a very coarse weight set (i.e. restricting biases to 0,
0.25, 0.5, 0.75, and 1) provides acceptable results. Using finer
resolution within the weight set usually results in a slightly higher
coverage, but at the expense of a much higher area overhead
Test Conference, 1990. Proceedings., International; 10/1990
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ABSTRACT: A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable.< >
IEEE Design and Test of Computers 05/1990; · 1.39 Impact Factor
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ABSTRACT: A description is presented of a serial interfacing technique for
embedded RAMs, which has been successfully applied to static single-port
and dual-port memories in custom integrated circuits. A single bit of
the input data path of a RAM (or a group of RAMs) is controlled by the
built-in self-test (BIST) circuit, and a single bit of the output data
path is observed during the execution of the algorithms. The other bits
are controlled and observed indirectly through the serial data path.
Automatically generated BIST circuits, which embed an algorithm suited
for the application with the RAM, have been developed. The serial data
path interface has also been used to provide external access to memories
on cost sensitive chips which could not justify the full BIST overhead.
This provides a simple external test access mode which uses a minimal
number of pins yet exercises the memory at full speed
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989; 06/1989
