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[show abstract]
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ABSTRACT: A highly advanced upgrade plan of the RIKEN AVF cyclotron is under way. The computation of the AVF electromagnetic fields was performed and successfully checked against the measurements. The following structural elements comprise the computer model of the machine: a beam buncher and two glazer lenses in the injection line, a magnet yoke, spiral sectors, central plugs, trim and harmonic coils, an inflector, an RF shield, RF dee electrodes, an electrostatic deflector, a magnetic channel, and a gradient corrector. Electric and magnetic field distributions and mechanical structures were transmitted to a beam dynamics code for simulations, in which particle losses on the surfaces of the system elements were estimated. The present study is focused on the AVF cyclotron electromagnetic fields that were used for the simulations of the AVF performance. New acceleration regimes were formulated with the help of the constructed computer model of the machine.
IEEE Transactions on Nuclear Science 07/2011; · 1.45 Impact Factor
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H. Ishiyama,
H. Miyatake,
N. Yoshikawa,
S. C. Jeong,
M. Wada,
Y. Ishida,
M. H. Tanaka,
S. Takaku,
Y. Fuchi,
H. Kawashima, [......],
H. Kawakami,
I. Katayama,
T. Nomura,
T. Teranishi,
M. Michimasa,
I. Imai,
Y. Yanagisawa, S. Kubono,
P. Strasser,
S. Kato
03/2003; -1:335-338.
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T. Ishii,
K. Oshima,
H. Sato,
S. Noda,
J. Kishimoto,
H. Kotani,
A. Nozoe,
K. Furusawa,
T. Yoshitake,
M. Kato,
M. Takahashi,
A. Sato, S. Kubono,
K. Manita,
K. Koda,
T. Nakayama,
A. Hosogane
[show abstract]
[hide abstract]
ABSTRACT: A 512-Mb flash memory, which is applicable to removable flash
media of portable equipment such as audio players, has been developed.
The chip is fabricated with a 0.18-μm CMOS process on a
126.6-mm<sup>2</sup> die, and uses a multilevel technique (2 bit/1
cell). The memory cell is AND-type, which is suitable for multilevel
operation. This paper reports new techniques adopted in the 512-Mb flash
memory. First, techniques for low voltage operation are described. The
charge pump, control of pumps, and the reference voltage generator are
improved to generate internal voltage stably for multilevel flash
memory. Next, a method for reducing total memory cost in the removable
flash media is described. A new operation mode named read-modify-write
is introduced on the chip. This feature makes the memory system simple,
because the controller does not have to track sector-erase information
IEEE Journal of Solid-State Circuits 12/2001; · 3.23 Impact Factor
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A. Nozoe,
H. Kotani,
T. Tsujikawa,
K. Yoshida,
K. Furusawa,
M. Kato,
T. Nishimoto,
H. Kume,
H. Kurata,
N. Miyamoto, S. Kubono,
M. Kanamitsu,
K. Koda,
T. Nakayama,
Y. Kouro,
A. Hosogane,
N. Ajika,
K. Koyashi
[show abstract]
[hide abstract]
ABSTRACT: A 256-Mb flash memory is fabricated with a 0.25-μm AND-type
memory cell and 2-bit/cell multilevel technique on a
138.6-mm<sup>2</sup> die. Parallel decoding of four memory threshold
voltage levels to 2-bit logical values prevents throughput degradation
due to multilevel operation. This parallel decoding has been achieved by
sense latches and data latches connected to each bitline. Tight
distribution of memory cell threshold voltage is essential to reliable
multilevel operation. This chip has several measures to deal with the
factors that widen the memory cell V<sub>th</sub>. The effect of
adjacent memory cell's V<sub>th</sub> is eliminated by using an AND-type
flash memory cell. An initial distribution width of 0.1 V is achieved.
The wordline voltage, which has negative temperature dependency,
compensates the positive dependency of memory cell V<sub>th</sub>. In
the -5-75°C range, memory threshold V<sub>th</sub> deviation is
reduced from the conventional 0.19-0.07 V. Conventionally, the number of
programs without erase operation per one sector is limited by the
limitations from program disturb. This chip introduced a new rewrite
scheme, and this limit is increased from the conventional 10-2048+64
times/sector
IEEE Journal of Solid-State Circuits 12/1999; · 3.23 Impact Factor
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A. Nozoe,
H Kotani,
T. Tsujikawa,
K Yoshida,
K Furusawa,
M Kato,
T Nishimoto,
H Kume,
H Kurata,
N. Miyamoio, S. Kubono,
I. Kanamitsu,
K Koda,
T Nakayama,
Y. Kouro,
A. Hosogane,
N. Ajika,
K Kobayashi
[show abstract]
[hide abstract]
ABSTRACT: A 256 Mb flash memory in 0.26 μm CMOS on a 138.6 mm<sup>2</sup> die uses a multilevel technique. The AND-type memory cell suitable for multilevel operation is used. One sector consists of(8192+256) memory cells. As two bits of data are stored in one physical cell, logical sector size is (16384+512)b. Sector erase and program times are both 1 ms/sector (2048+64B), so typical programming rate is 2 MB/s. By increasing sector size to four times that in conventional two-level flash memories, program throughput is kept acceptable for mass-storage applications, even with multi-level operation
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International; 02/1999
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M. Tomizawa,
S. Arai,
Y. Arakaki,
Y. Hashimoto,
A. Imanishi,
S.C. Jeong,
I. Katayama,
T. Katayama,
H. Kawakami, S. Kubono, [......],
T. Nomura,
M. Okada,
M. Oyaizu,
Y. Shirakabe,
P. Strasser,
Y. Takeda,
J. Tanaka,
M.H. Tanaka,
E. Tojyo,
M. Wada
[show abstract]
[hide abstract]
ABSTRACT: The first acceleration test of a radioactive nuclear beam was
performed in a radioactive beam facility at INS. The <sup>19</sup>Ne
beam was produced by bombarding a LiF target with 30 MeV protons from an
SF cyclotron, and ionized by a ECR ion source. We succeeded to
accelerate the <sup>19</sup>Ne<sup>2+</sup> ions to 0.72 MeV/u by
heavy-ion linacs. The intensity delivered to a secondary target is not
yet enough. Further improvements will be done to perform experiments
using accelerated radioactive nuclei
Particle Accelerator Conference, 1997. Proceedings of the 1997; 06/1997
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I. Katayama,
T. Nomura,
S. Arai,
Y. Arakaki,
Y. Hashimoto,
A. Imanishi,
S. C. Jeong,
T. Katayama,
H. Kawakami, S. Kubono, [......],
P. Strasser,
Y. Takeda,
J. Tanaka,
M. H. Tanaka,
E. Tojyo,
M. Tomizawa,
M. Wada,
S. Kato,
T. Shinozuka,
H. Wollnik
[show abstract]
[hide abstract]
ABSTRACT: A Radioactive beam facility using a thick target, an ISOL and heavy ion linacs will soon come into operation at INS, University of Tokyo. The status of the project together with experimental programs are reported. © 1997 American Institute of Physics.
AIP Conference Proceedings. 02/1997; 392(1):433-436.
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A. Nozoe,
T. Yamazaki,
H. Sato,
H. Kotani, S. Kubono,
K. Manita,
T. Tanaka,
T. Kawahara,
M. Kato,
K. Kimura,
H. Kume,
R. Hori,
T. Nishimoto,
S. Shukuri,
A. Ohba,
Y. Kouro,
O. Sakamoto,
A. Fukumoto,
M. Nakajima
[show abstract]
[hide abstract]
ABSTRACT: A 3.3 V single-supply 32 Mb flash memory realizing a 512B per
sector program/erase unit features serial sector read, sector program
and sector erase modes. By using AND cells and connecting one sense and
latch (SL) circuit to every data line (DL) pair, these modes can handle
data strictly sector by sector (512B). The same sector size for both
programming and erasing simplifies the rewrite operation to a small
number of sectors and prevents system performance degradation. The chip
is implemented in a 0.45 μm triple-well CMOS process
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International; 03/1995
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K. Sato,
K. Kenmizaki, S. Kubono,
T. Mochizuki,
H. Aoyagi,
M. Kanamitsu,
S. Kunito,
H. Uchida,
Y. Yasu,
A. Ogishima,
S. Sano,
H. Kawamoto
[show abstract]
[hide abstract]
ABSTRACT: A 4-Mb pseudo static RAM (PSRAM) suitable for universal battery
usage is described. The wide voltage range, 2.6±1 V, is set to
target the power supply voltage of the PSRAM considering various voltage
levels and charging-discharging characteristics of batteries. A
double-to-single automatically switchable booster is developed to
provide the wide voltage range operation. To reduce the power
dissipation of data retention for battery usage a low-power back-bias
generator with a new substrate-level sensor and a temperature-dependent
self-refresh timer with a unique internal refresh control scheme are
demonstrated. A PSRAM operation ranging from 1 V to more than 5 V was
obtained and a 3-μA data retention current was realized at room
temperature in contrast with 7 μA at 70°C and V <sub>cc
</sub> of 2.6 V. This PSRAM allows a 20-Mbyte RAM disk to retain data
for two months with a single lithium battery
IEEE Journal of Solid-State Circuits 12/1991; · 3.23 Impact Factor
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K Sato,
T. Kajimoto,
H Kawamoto,
K. Kenmizaki, S. Kubono,
T Mochizuki,
H Aoyagi,
M. Kanamitsu,
S. Kunito,
S Sano,
A. Ogishima
Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International; 03/1991
