[Show abstract][Hide abstract] ABSTRACT: Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architec-tures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed architecture is parametrizable for any number of iterations without adding hardware complexity. The SCAN decoder architecture is compared to another soft-output decoder that implements a Belief Propagation (BP) algorithm. The SCAN decoder can reach a higher throughput than a BP decoder, with a lower memory footprint. Moreover, only one iteration with the SCAN algorithm leads to better decoding performance than 50 iterations of the BP algorithm.
Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, Edited by Mourad Fakhfakh, Esteban Tlelo-Cuautle, Patrick Siarry, 08/2015: chapter 7; SPRINGER., ISBN: 978-3-319-19871-2
[Show abstract][Hide abstract] ABSTRACT: In this paper two iterative interpolation algorithms proposed in the scientific literature for estimating the frequency of complex-valued sine-waves are generalized to a generic Maximum Sidelobe Decay (MSD) window in order to achieve highly accurate estimates even when real-valued pure or harmonically distorted sine-waves are analyzed. The analytical expressions for the frequency estimations formulas are derived. Moreover the accuracy achieved when pure, noisy, and noisy and harmonically distorted sine-waves are analyzed is compared with those provided by the classical Interpolated Discrete Fourier Transform (IpDFT) and three-point IpDFT algorithms through computer simulations. The performed comparison allows us to determine in which situations the proposed algorithms can be advantageously used.
[Show abstract][Hide abstract] ABSTRACT: A novel frequency band decomposition architecture based on a single-bit 4th order sigma delta modulators and intended for a software defined radio receiver is presented in this paper. The parallel designed architecture is flexible with parallel programmable branches. Synthesis results prove that this architecture satisfies the multistandard receiver specifications without the use of automatic gain control circuit. Nevertheless, system level analysis of the mixed baseband architecture using a single passive anti-aliasing filter has revealed adjacent branch interference problems. A design specification for a non-unitary signal transfer function for sigma delta modulators is proposed to cover interferences of adjacent branches.
2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC); 05/2014
[Show abstract][Hide abstract] ABSTRACT: This paper proposes a three-point Interpolated Discrete Fourier Transform (IpDFT) method for frequency estimation of a discrete-time sinusoidal signal. It is based on the maximum sidelobe decay (MSD) windows and is highly effective in rejecting the detrimental effect on the estimation accuracy due to the image component of the signal spectrum. This remarkable feature is achieved by using an analytical expression based on a suitable weighting of the three largest DFT spectrum samples. The proposed method provides good results when the effect of the spectral interference due to the image component dominates other estimation error sources. The accuracy of the proposed method and of other state-of-the-art methods such as the multi-point IpDFT methods and the four-parameter sine-fitting (4PSF) algorithm are compared through both computer simulations and experimental results in the case of ideal, noisy, and harmonically distorted sinusoids. A small number of acquired cycles is assumed in order to analyze situations in which the contribution from the image component interference is significant. The performed comparison shows that the proposed method outperforms the considered multi-point IpDFT methods when the Signal-to-Noise Ratio (SNR) is higher than 30 dB and the number of acquired cycles is enough small. The proposed method outperforms also the 4PSF algorithm when the frequency estimation error is dominated by harmonics rather than wideband noise.
Digital Signal Processing 01/2014; 24(1):162–169. DOI:10.1016/j.dsp.2013.09.014 · 1.26 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The chapter is dedicated to dynamic testing of Analog-to-Digital Converters (ADCs) by means of both time- and frequency-domain sine-fitting algorithms (SFAs). At first the sine-fitting procedure used for the estimation of SIgnal-to-Noise And Distortion ratio (SINAD) and Effective Number Of Bits (ENOB) parameters is described. In the following the expressions for the bias and the standard deviation of the ENOB estimator provided by a SFA are derived. Then, the SFAs based on the Interpolated Discrete Fourier Transform (IpDFT) method, the Energy-Based (EB) method, and the well known three- and four-parameter SFAs are separately analyzed. For each algorithm, the basic theoretical background and the operational detail are given. Moreover, the accuracy of all the presented algorithms are compared by means of both theoretical and simulation results. Some aspects concerning the influence of the harmonics, time jitter, and time base distortions on the dynamic performance of an ADC are also discussed. Besides, some Multi-Harmonics Sine-Fitting Algorithms (MHSFAs) are briefly described. Finally, the accuracy of the ENOB estimates provided by the considered SFAs and MHSFAs are compared through real-world data.
[Show abstract][Hide abstract] ABSTRACT: Polar codes are the first error-correcting codes to provably achieve the
channel capacity but with infinite codelengths. For finite codelengths the
existing decoder architectures are limited in working frequency by the partial
sums computation unit. We explain in this paper how the partial sums
computation can be seen as a matrix multiplication. Then, an efficient hardware
implementation of this product is investigated. It has reduced logic resources
and interconnections. Formalized architectures, to compute partial sums and to
generate the bits of the generator matrix k^n, are presented. The proposed
architecture allows removing the multiplexing resources used to assigned to
each processing elements the required partial sums.
[Show abstract][Hide abstract] ABSTRACT: Polar codes are a new family of error correction codes for which efficient
hardware architectures have to be defined for the encoder and the decoder.
Polar codes are decoded using the successive cancellation decoding algorithm
that includes partial sums computations. We take advantage of the recursive
structure of polar codes to introduce an efficient partial sums computation
unit that can also implements the encoder. The proposed architecture is
synthesized for several codelengths in 65nm ASIC technology. The area of the
resulting design is reduced up to 26% and the maximum working frequency is
improved by ~25%.
[Show abstract][Hide abstract] ABSTRACT: This paper deals with an accurate and fast sine-wave frequency estimation procedure suitable for real-time applications where measurement latency is an issue. The procedure compensate the detrimental effect due to spectral interference from the fundamental image component that adversely affects the frequency estimates provided by the classical Interpolated Discrete Fourier Transform (IpDFT) method when a very small number of sine-wave cycles is acquired. The accuracies of the frequency estimators provided by the proposed procedure and the classical IpDFT method are compared through both computer simulations and experimental results in the case of pure sine-waves or sine-waves affected by wideband noise and harmonics. The procedure is simple to understand and to apply. The required processing effort is low and quite close to the effort required by the classical IpDFT method.
2013 IEEE 7th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS); 09/2013
[Show abstract][Hide abstract] ABSTRACT: Abstract-This paper presents a model of a Wheatstone bridge sensor in VHDL-AMS. This
model is useful to take into account the temperature effect on the sensor accuracy. The
model is developed on the basis of a resistor model. Simulations are performed for three
different combinations of parameters values. They confirm the resistors mismatch effect on
the sensor accuracy in high temperature (HT).
Keywords: Wheatstone bridge, sensor, resistance, mismatch, high temperature, VHDL-AMS
19th International Measurement Confederation (IMEKO) Symposium, Technical Committee Measurement of Electrical Quantities (TC 4), Barcelona Spain; 07/2013
[Show abstract][Hide abstract] ABSTRACT: This paper, proposes a new architecture to reduce the silicon area of the Cartesian feedback (CFB) used to linearize a power amplifier in WCDMA communication standard. The first stage of the previous version consists of two CORDIC structures in vector mode for the phase computation following by a subtractor. Here, we propose to merge these two CORDIC structures to obtain directly the phase difference between the feedback and the direct paths. This approach allows reducing the silicon area as well as the power consumption.
New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International; 06/2013
[Show abstract][Hide abstract] ABSTRACT: Abstract— In modern era the utilization of battery empowered systems is growing exponentially. In the goal to achieve an optimal system performance, the employment of a BMS (Battery Management System) is inevitable. The recent sophistications in the area of BMSs are demanding more and more processing resources. Reducing the BMS power consumption is becoming one of the most difficult industrial challenges. Most of efforts to achieve this goal are focused on improving the embedded systems design, but very few studies target to exploit the input signal time-varying nature. This work aims to achieve power efficiency by smartly adapting the system activity to the input signal local variations. In this context a novel A/D conversion approach is derived. The proposed solution, based on the LCSS (Level Crossing Sampling Scheme) presents an ADC (A/D Converter), able to adapt its acquisition rate according to the input signal variations. In fact, the principle is to smartly exploit the signal local characteristics to acquire only the relevant signal parts at relevant sampling rate. The idea offers a significant reduction in acquired number of samples and hence promises a drastic reduction in the system power consumption compared to the classical approach.
Keywords— Low power consumption, Level crossing sampling, Signal driven A/D conversion, Non-uniform thresholds, Li-Ion battery.
IEEE International Instrumentation and Measurement Technology Conference (I2MTC),, Minneapolis MN, USA.; 05/2013
[Show abstract][Hide abstract] ABSTRACT: This paper analyzes the performance provided by the three-parameter sine-fit (3PSF) and the four-parameter sine-fit (4PSF) algorithms when estimating the noise power of a sine wave corrupted by a white Gaussian noise. In the former case, the frequency parameter is extracted from the available data by using the interpolated discrete Fourier transform (IpDFT) method. The related procedure is called the 3PSF-IpDFT algorithm. Simple expressions for the expected sum-squared fitting and the expected sum-squared residual errors are derived for both the 3PSF and 4PSF algorithms, which agree with previously published results. These expressions show that the sum-squared fitting error of the 4PSF algorithm is smaller than the corresponding value associated with the 3PSF algorithm when the uncertainty of the sine-wave frequency employed by the latter algorithm is greater than the related Cramér-Rao lower bound. From this point of view, the 4PSF algorithm outperforms the 3PSF-IpDFT algorithm. However, since the frequency estimator provided by the IpDFT method is consistent, the sum-squared fitting error associated with both the 3PSF-IpDFT and 4PSF algorithms can be made negligible as compared with the sum-squared residual errors, when the number of analyzed samples is large enough. Moreover, several simulation results show that the 3PSF-IpDFT algorithm requires a much lower computational effort than the 4PSF algorithm. Therefore, it represents the best alternative when estimating the noise power of a sine wave embedded in white noise.
IEEE Transactions on Instrumentation and Measurement 12/2012; 61(12):3234-3240. DOI:10.1109/TIM.2012.2205511 · 1.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA zero-intermediate frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feed-back I/Q demodulator, and a digital stage adjusting the phase rotation around the loop. The whole system con-sumes 500 and 2.94 mW, respectively, for the analog and the digital part. System level simulation gave a maximum improvement of 35 dBc at 5 MHz from the carrier for the W-CDMA signal.
[Show abstract][Hide abstract] ABSTRACT: This paper describes the effect of the spectral interference and wideband noise on the accuracy of the sine-wave frequency estimator provided by the Interpolated Discrete Fourier Transform (IpDFT) method based on some commonly used cosine windows. It is shown that the spectral interference contribution from the image component has a sinusoidal behaviour with respect to the sine-wave phase and the expression for its amplitude is derived. Also, a simple expression for the variance of noise contribution is derived. Based on the achieved results, the Probability Density Function (PDF) of the sine-wave frequency estimator is obtained. The accuracy of each expression derived in the paper is verified by means of computer simulations. Furthermore, the accuracy of the PDF of the sine-wave frequency estimator is verified by means of experimental results.