-
[show abstract]
[hide abstract]
ABSTRACT: A class-C power amplifier (PA) for operation as an antenna interface in body sensor network (BSN) applications is presented. It is fabricated in a 0.13 μm RF CMOS process for operation in the 400 MHz MedRadio band. It achieves a measured peak output power of -4 dBm and drain efficiency of 43%.
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE; 07/2011
-
[show abstract]
[hide abstract]
ABSTRACT: Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two well-known limitations: slow convergence and increased computational complexity/power dissipation for higher adaptive filter orders and sampling frequencies. Half (f<sub>s</sub>/2) and quarter-rate (f<sub>s</sub>/4) LMS calibration for oversampled A/D decimators are used to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (ΣΔ) ADC. Energy savings up to 30% compared to conventional full-rate (f<sub>s</sub>) schemes are confirmed using an Altera Stratix II field programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2-2 cascade ΣΔ ADC implemented in 0.13 μm CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the ΣΔ ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.
Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on; 06/2011 · 4.63 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: This paper introduces an EER 90 nm CMOS experimental prototype switched capacitor power amplifier (SCPA) that achieves high output power, efficiency and linear output-power control using a switched-capacitor-based switching PA without the use of a supply modulator. While amplifying 64-QAM OFDM modulation with a 20 MHz signal bandwidth it achieves an average output power of 17.7 dBm, an average PAE of 32.1%, and an EVM of 2.9%.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
-
[show abstract]
[hide abstract]
ABSTRACT: The relentless scaling of CMOS circuits has led to the possibility of completely integrated RF-SOCs, including the PA. A CMOS PA likely will not achieve the same peak output power and efficiency as its counterpart in a III-V technology. It is conceivable, however, that by taking advantage of the strengths of CMOS switching devices, future CMOS PAs can win in terms of average efficiency and, perhaps more importantly, cost. PWM techniques offer one such potential solution, owing to the level of digital integration possible. Because of this, PWM PAs are expected to scale well, and the dynamic range possible with such amplifiers should increase as well because the faster devices will be able to process signals with smaller pulse widths.
IEEE Microwave Magazine 03/2011; · 2.11 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: In high-speed communications systems, the power amplifier (PA) is the dominant source of power consumption from the battery and, thus, one of the main limitations in increased mobility. Switching PAs are more efficient than their linear counterparts and, thus, demand less power from the battery; however, they do not have sensitivity to the amplitude variations seen in nonconstant-envelope modulation. This brief discusses supply modulation, a technique that enables use of switching PAs for improved power efficiency, by providing a means of linearizing the PA.
Circuits and Systems II: Express Briefs, IEEE Transactions on 08/2010; · 1.41 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: An area-efficient U-shaped slow-wave coplanar waveguide (U-SCPW) in a standard 0.18 μm CMOS process is presented. Compared to a conventional straight line CPW (S-CPW), it provides a more compact layout because of its approximate 1:1 aspect ratio. Measured results show that it has a quality factor and phase velocity comparable to its straight-line counterpart with measured Q ~ 30 at 23 GHz.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
-
[show abstract]
[hide abstract]
ABSTRACT: A fully-integrated LNA in 0.18/xm CMOS simultaneously achieves high gain, low noise figure (NF), good third-order input intercept linearity (IIP3), and low DC bias current consumption: 19 dB, 2.4 dB, -14.2 dBm and 1.3 mA, respectively, from a 1.2 V supply. The single-ended LNA uses a common-gate common-source (CG-CS) topology and operates at 5.4 GHz for WLAN applications. Using g<sub>m-</sub>boosting, current-reuse and transformer-feedback techniques, the LNA mitigates several design issues seen in the widely used common-source common-source current-reuse (CS-CS) LNAs and improves the IIP3 of CG-CS schemes by 6 dB, without increasing power and area consumption.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
-
[show abstract]
[hide abstract]
ABSTRACT: A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT ΣΔ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ 1 MHz frequency offset with quadrature error less than 1°.
IEEE Journal of Solid-State Circuits 04/2010; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A pipelined analog-to-digital converter (ADC) uses switched-capacitor stages that settle in two steps that occur sequentially in time. The first step of settling places charge onto the load capacitance using charge pumps, and the second fulfills the settling requirements using typical negative feedback around an operational amplifier. Hence, the design combines the efficiency of a fast charge-transfer phase with the gain and noise-immunity advantages of amplifier-driven settling. Improved conversion efficiency results from a higher ratio of current delivered to the load to that consumed in static biasing. Additional circuitry constrains critical amplifier node voltages during the charge transfer, facilitating a graceful transition to amplifier-driven settling. The two-step settling technique is demonstrated in a 2.5 bit/stage 10-bit pipelined ADC that consumes 11.1 mW while sampling a 21.3 MHz input signal at 42 MS/s. The resulting SNDR is 55.6 dB (ENOB = 8.94) and the SFDR is 67.5 dB.
IEEE Journal of Solid-State Circuits 03/2010; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A system is proposed to allow the phase and amplitude of a signal to be accurately set and regulated over process and power supply variations. It uses a variable gain amplifier (VGA) in conjunction with the phase shifter to compensate for the variable losses of the phase shifter and simultaneously provide a means of adjusting the amplitude of the signal. The system has been fabricated in a 0.18 ??m CMOS process, and operates at 1.9 GHz. The phase can be set with 5 bits of control over a 240?? range and the amplitude can be varied over a 20 dB range. The feedback loops reduce the variation in | S <sub>21</sub>| across the phase control range from 12.1 to 0.4 dB. For a changing power supply voltage the feedback loops reduce the maximum phase deviation from 28?? to 7?? , and across different test chips the maximum standard deviation over the phase control range is reduced from 12?? to 3??.
Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2010; · 1.97 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A class-G supply modulator utilizes parallel low- dropout (LDO) regulators that are controlled by comparators and negative feedback. It optimizes the power consumption of a nonlinear power amplifier (PA) operating with supply modulation, such that it draws current from one of multiple appropriately sized supply voltages as determined by the input signal envelope. The class-G modulator is used in conjunction with a class-E PA operating in an envelope elimination and restoration (EER) mode to efficiently amplify signals with large peak-to-average ratios. The measured maximum output power and power added efficiency (PAE) are 29.3 dBm and 69%, respectively. The class-G technique is demonstrated for a 64 QAM, OFDM input signal (symbol period = 4 mus) wherein the measured error vector magnitude (EVM) is 2.5% and the average efficiency of 22.6%.
IEEE Journal of Solid-State Circuits 10/2009; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A class-G PA consisting of a class-E PA and class-G supply modulator is fabricated in a 130 nm process. It operates from 1.65 and 3.3 V supplies and the die area is 2times2 mm. It achieves a measured Pout of 29.2 dBm with a PAE of 72%. It can amplify signals with peak-to-average ratios of ~3-20 dBm, or act as power control for constant envelope signals. It achieves an EVM value of 4.6%-rms for a root-raised cosine filtered, QPSK modulated signal similar to that specified in the WCDMA standard (Data rate = 3.84 MB/s) and an average efficiency of 45%, compared to 17% for a similar class-B PA.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
-
[show abstract]
[hide abstract]
ABSTRACT: A quadrature voltage-controlled oscillator (QVCO) based on the time-varying gate-modulated coupling of two LC tank VCOs is introduced. Using a standard 0.18 mum CMOS process, the new topology is compared to the conventional series QVCO in terms of start-up loop gain, quadrature phase accuracy, phase noise, tuning range, and voltage headroom characteristics. In addition to comparable phase noise performance, the gate-modulated QVCO (GM-QVCO) also exhibits superior quadrature phase accuracy, and suitability for low power supply voltage designs that use cascode current sources and active loads. It draws 2.4 mA from a 1.8 V power supply, displays a phase noise of -122 dBc/Hz @ 1 MHz offset, and has a quadrature phase error of 0.4deg.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
-
[show abstract]
[hide abstract]
ABSTRACT: Efficient power delivery is a challenge in many RF systems. The use of space-time block codes as a means for reducing the required output power of the power amplifier and thereby improving the system efficiency is described. The first implementation of a fully-integrated 4-antenna transmitter based on space-time block codes is described. It is fully configurable as a 1-, 2-, 3-, and 4-antenna system to investigate the tradeoffs between space-time block code length and overall system efficiency. It is shown that the measured optimum is a 3-antenna system capable of delivering +27.7 dBm into a 50 Omega load using three class-AB power amplifier cells each delivering +20 dBm into 50 Omega with a PAE of 23%. Owing to the space-time block coding gain, the overall PAE of the 3-channel transmitter delivering +27.7 dBm is 39%. The system is intenerated in 0.18 mum CMOS and measures 4 mm times 6 mm.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
-
[show abstract]
[hide abstract]
ABSTRACT: A class-E power amplifier (PA) utilizes differential switches and a tuned passive output network improves power-added efficiency (PAE) and insensitivity to amplitude variations at its input. A modulator is introduced that takes outphased waveforms as its inputs and generates a pulse-width and pulse-position modulated (PWPM) signal as its output. The PWPM modulator is used in conjunction with a class-E PA to efficiently amplify constant envelope (e.g., GMSK) and non-constant envelope (e.g., QPSK, QAM, OFDM) signals with moderate peak-to-average ratios (PAR). The measured maximum output power of the PA is 28.6 dBm with a PAE of 28.5%, and the measured error vector magnitude (EVM) is 1.2% and 4.6% for GMSK and pi/4-DQPSK (PAR ap 4 dB) modulated signals, respectively.
IEEE Journal of Solid-State Circuits 07/2009; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Dynamic spectrum access (DSA) is a promising approach for the more effective use of existing spectrum. Of fundamental importance to DSA is the need for fast and reliable spectrum sensing over a wide bandwidth. A model for two-stage sensing is described based on an analysis of the mean time to detect an idle channel. Simulation results show that it provides significantly faster idle channel detection than conventional single-stage random searching. Several system-level issues are also investigated including the settling time of the phase-locked loop (PLL) in the frequency synthesizer, which determines the channel switching time. Effects of the bandwidth of the coarse sensing block and the integration duration of the energy detector are also presented.
IEEE Transactions on Wireless Communications 07/2009; · 2.59 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is > 55 dB over a 200 MHz bandwidth centered around 5.25 GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, -79 dBm sensitivity, 5.6 dB SSB NF,-7 dBm IIP3, -18 dB S<sub>11</sub> and a 1 mm times 2 mm die area in 0.18 mum CMOS.
IEEE Journal of Solid-State Circuits 06/2009; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Parasitic magnetic coupling is a major design challenge for integrated circuit designers. Fundamentally, it originates in conventional spiral inductors because the magnetic field is not localized, extending far beyond the perimeter. This paper introduces a twisted winding scheme for inductors that increases the localization of the magnetic field, reducing parasitic magnetic coupling by as much as 3100X and the edge-to-edge spacing of inductors by 10X. These results are validated in a 0.18 mum CMOS process.
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE; 10/2008
-
[show abstract]
[hide abstract]
ABSTRACT: Time-domain responses of wideband CMOS amplifiers using several inductive peaking techniques are presented. Transient performance considerations are described, including the effects of transistor parasitics on settling and edge rates. A combination of time-and frequency-domain performance is derived for a given bandwidth extension technique, and tradeoffs are discussed. Measured results for several high-speed high-gain single-stage amplifiers are presented in 0.18-mum CMOS, and a design strategy for multistage amplifiers is introduced. Finally, design and simulation results are presented for a multistage amplifier in 0.18-mum CMOS that attains a bandwidth of 22.7 GHz with 14.7-dB voltage gain, operates at 40 Gb/s, and consumes 93.6 mW.
Circuits and Systems I: Regular Papers, IEEE Transactions on 09/2008; · 1.97 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The origins and detrimental effects of charge injection in charge-pump PLLs are discussed. Standard topologies for minimizing charge injection are discussed, and a new charge- pump topology with virtually zero charge injection is presented. Simulation results are presented to compare the performance of the proposed topology with standard designs, and it is shown that the new topology minimizes the steady state phase offset.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
