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ABSTRACT: In the use of single/few electrons in distributed storage for nonvolatile, low power and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has a radic n dependence and we are working with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and evaluate the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of low doped drain (LDD) process is investigated to draw these conclusions.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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ABSTRACT: The polarity of gates and the threshold voltages are primary parameters that determine the electric fields in the gate stack region of non-volatile memories. This field is central to programming, retention and the other characteristics of the devices. We have investigated the effect of the gate polysilicon polarity, experimentally, for silicon-oxide-nitride-oxide-silicon (SONOS) memory devices on silicon-on-insulator (SOI) wafers. An ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention in our structures. The effect of ONO film, grown and deposited and of doping was simulated and characterized. Retention is affected by the electric field between the control gate and the storage node. Our experiments and simulations verify the consequences of different polarity of control gates through the change in electric field that they cause in retention and erase times for n+ and p+ polysilicon gate SONOS memories is verified through the characteristic energies of the processes.
MRS Proceedings. 12/2006; 997.
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ABSTRACT: We report the operational characteristics of ultrashort SONOS memories down to ∼30-nm effective gate length. Good sub-threshold swing, good drain-induced barrier lowering (∼120 mV/decade), and ∼2.4 V of memory window down to the smallest dimensions demonstrate the improvements that result from a thin tunneling oxide and a large trapping center density. The use of distributed defects and thin tunneling oxide is reflected in a memory window that is stable up to at least 10<sup>5</sup> cycles for the smallest devices. The smallest structures tested employ ∼75 electrons for memory storage, which allows for device to device reproducibility. The capture and emission processes asymmetries point to the differences in the energy parameters of the two processes. The smallest structures, however, do show loss of retention time compared to the larger structures, for the same oxide-nitride-oxide stack thickness, and this is believed to arise from higher leakage due to higher defects distribution in the gate insulators from process-induced damage. All tested devices, down to ∼30-nm effective gate length, show very good endurance characteristics.
IEEE Transactions on Nanotechnology 01/2005; · 2.29 Impact Factor
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Sanghun Jeon,
S. Choi,
H. Park,
Hyunsang Hwang,
Jung Hee Han,
Hisun Chae,
Soo Doo Chae,
Ju Hyung Kim,
Moon Kyung Kim,
Youn Seok Jeong,
Yoondong Park,
Sunare Seo,
Jo Won Lee, Chung Woo Kim
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ABSTRACT: In this article, we report on electrical and memory properties of triple high-κ stacks (Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>) with high pressure (10 atm) H<sub>2</sub> and D<sub>2</sub> annealing for SONOS type flash memory device applications. For 3 nm-thick Al<sub>2</sub>O<sub>3</sub>/10 nm-thick HfO<sub>2</sub>/10 nm-thick Al<sub>2</sub>O<sub>3</sub> (AHA) stack, memory window (M.W.) of 1.4 V at programming/erasing (P/E) condition of ±6 V/1-2 msec was obtained. In addition, high pressure D<sub>2</sub> annealed sample shows improved retention characteristics such as large memory window, and low slope per decade with retention time.
Nanotechnology, 2004. 4th IEEE Conference on; 09/2004
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ABSTRACT: In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.
IEEE Transactions on Nanotechnology 01/2004; · 2.29 Impact Factor
