Chun-Hung Yang

National Cheng Kung University, 臺南市, Taiwan, Taiwan

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Publications (15)12.51 Total impact

  • Chien-Hung Tsai · Chun-Hung Yang · Jiunn-Hung Shiau · Bo-Ting Yeh ·
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    ABSTRACT: This paper presents a multimode digital controller with dead-time self-exploration (DTSE) for synchronous buck converters that simultaneously achieves high efficiency and a fast transient response. The automatic mode switching technique uses the duty-cycle command to determine multimode operation without sensing any current signals. The DTSE algorithm is used to minimize the steady-state duty-cycle command to maximize the converter efficiency. During load transients, a nonlinear control mode is employed to reduce the transient response. The proposed digital controller is fabricated in a CMOS 0.18-μm process. The experimental results for a 1.2-V output voltage show that the measured power efficiency is higher than 85% for a load range of 10-600 mA and that the measured transient response is improved by 28% compared to that of the traditional voltage-mode converter.
    IEEE Transactions on Power Electronics 04/2014; 29(4):1830-1839. DOI:10.1109/TPEL.2013.2265297 · 6.01 Impact Factor
  • Chien-Hung Tsai · Chun-Hung Yang · Jui-Chi Wu ·
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    ABSTRACT: This paper presents the use of a combined random pulse position modulation (RPPM)/digital pulsewidth modulation (DPWM) digital controller for a buck converter to simultaneously achieve low-conductive electromagnetic interference (EMI) and a fast transient response. An area-efficient RPPM/DPWM controller suitable for advanced system-on-chip integration is proposed and implemented in a field-programmable gate array-based prototype to verify its EMI-suppression capability. The experimental results for a 1.2-V digital buck converter show that the proposed digital switching regulator can switch between RPPM and DPWM modes smoothly and automatically. Closed-loop system measurements demonstrate that, compared to DPWM, up to 17.27 and 14.99 dB power spectra reductions are obtained in the input current and switching node, respectively.
    IEEE Transactions on Industrial Electronics 09/2013; 60(9):3938-3947. DOI:10.1109/TIE.2012.2207650 · 6.50 Impact Factor
  • Bo-Ting Yeh · Chun-Hung Yang · Kai-Cheung Juang · Chien-Hung Tsai ·
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    ABSTRACT: This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.
    VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on; 04/2013
  • Huei-Shan Chen · Chun-Hung Yang · Chien-Hung Tsai · Guan-Lin Li ·
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    ABSTRACT: A window delay-line analog-to-digital converter (ADC) with programmable resolutions for digitally-controlled switch-mode power supplies (SMPS) used in low-power portable applications is proposed in this paper. Due to its simple, low-power architecture and small silicon area, this ADC can be fully integrated with a digital controller. The proposed ADC quantizes the output converter voltage within a window of the reference voltage. The ADC has been fabricated in a TSMC 0.18μm CMOS technology and verified as a part of a 976.56 KHz, 3.6 to 1.2 V buck DC-DC converter.
    Control and Modeling for Power Electronics (COMPEL), 2012 IEEE 13th Workshop on; 01/2012
  • Chun-Hung Yang · Chin-Wei Mu · Chien-Hung Tsai ·
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    ABSTRACT: This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines' process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.
    01/2011; DOI:10.1109/IECON.2011.6119550
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    Jun-Yan Liu · Chun-Hung Yang · Chien-Hung Tsai ·
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    ABSTRACT: This paper presents a design procedure using the correlation-based identification to determine the compensation coefficients. A method for verifying the compensation coefficients is also proposed. That solved the open-loop frequency response of digitally controlled switched-mode power supply is difficult to accurately measure and provided a method to test the function of digital compensators. Experimental results show that the open-loop and closed-loop frequency responses obtained using the correlation-based identification method are close to the measured frequency responses.
    01/2011; DOI:10.1109/PEDS.2011.6147405
  • Jia-Hui Wang · Chun-Hung Yang · Chien-Hung Tsai ·
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    ABSTRACT: The design of a low-voltage fast-transient low-dropout regulator (LDR) with a current feedback buffer (CFB) for system-on-ship (SoC) applications is presented. When the CFB senses variation in the load current, it quickly controls the power transistor to achieve fast-transient and small output voltage variation. The proposed LDR has high current efficiency because the CFB can adjust the quiescent current at various load currents. A 1 V capacitor-less LDR with a 1.2 V power supply was fabricated in 0.35 μm CMOS technology. The CFB improves the current efficiency from 66.5% to 99% in light load.
  • Chun-Hung Yang · Jiunn-Hung Shiau · Chien-Hung Tsai ·
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    ABSTRACT: This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the 10-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental results show that the linear range of voltage is obtained from 0.4 to 3V and the step response between 0.9 and 1.2 V is equal to 1.5 μs, thus validating the functionality of the mixed-level model. Further verification is found by the experimental results being equivalent to the simulation results.
  • Chun-Hung Yang · Chun-Nan Liu · Chien-Hung Tsai ·
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    ABSTRACT: This paper presents a direct digital algorithm for digital PID-controlled switched-mode power supplies (SMPS). The crossover frequency and phase margin of the closed-loop system can be set using the proposed approach. The algorithm determines the PID controller parameters, and in the proposed procedure is clearly. The algorithm also takes into account the integral gain to prevent limit-cycle oscillation (LCO). Experimental results demonstrate that the proposed algorithm is suitable for voltage-mode CCM buck converter.
  • Chun-Nan Liu · Chun-Hung Yang · Chien-Hung Tsai ·
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    ABSTRACT: This paper presents a methodology to design a PID Digital Compensator for digital controller power electronics systems. This method is base on direct digital design and use on digital controller buck dc-dc converter. Crossover frequency and phase margin of close-loop system can be set by this method, and the integration coefficient in digital compensator set by this method can be avoid one of the LCO(Limit Cycle Oscillation) condition.
  • Jui-Chi Wu · Chin-Wei Mu · Chun-Hung Yang · Chien-Hung Tsai ·
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    ABSTRACT: A fully digital controlled low-EMI switching converter combining RPPM (random pulse position modulation), our improved version of hybrid DPWM (digital pulse width modulator) and AEDPWM (area-efficient DPWM) schemes is proposed to achieve low-EMI (electromagnetic interference) with reduced area and power consumption. A FPGA-controlled prototype buck converter operating at 1 MHz switching frequency with 1.8 V input voltage and 0.6-1.2V output voltage is presented to demonstrate the technique. The resulting switching noise suppression capability is up to 18 dB in average.
    Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian; 12/2009
  • Pui-Kei Leong · Chun-Hung Yang · Chi-Wai Leng · Chien-Hung Tsai ·
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    ABSTRACT: This paper describes the complete design and implementation of a low-power sigma-delta DPWM (Sigma-Delta DPWM) controller for switching converter which can operate at a very high frequency. In the previous design approach, the effective resolution of Sigma-Delta DPWM, i.e. the effective number of bit (ENOB) is over-estimated by using the conventional signal-to-noise ratio (SNR) with a continuous-time sine-wave input. Therefore, the modified expressions of SNR and ENOB are presented, which are suitable for the digital sigma-delta modulator (Sigma-Delta MOD) with a discrete-time discrete-amplitude signal. In addition, the trade off between the hardware area consumption and the SNR value is discussed. Finally, the system simulation results of the general 10-b DPWM controller and 10-b effective resolution SigmaDelta DPWM controller for buck converter are shown to verify the proposed design approach.
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009
  • Hung-Yuan Chu · Chun-Hung Yang · Chi-Wai Leng · Chien-Hung Tsai ·
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    ABSTRACT: This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) DeltaSigma modulator which can improve the design procedure. The proposed top-down, mixed-level design platform is implemented under Cadencepsilas Spectre environment using Verilog-A. A 2<sup>nd</sup> order CT BP DeltaSigma modulator for WCDMA applications. The central frequency of this modulator is at 100 MHz and the quantizer operates at 400 MHz clock frequency. The modulator is designed using TSMC 0.35 mum CMOS technology with a supply voltage of 3.3 V. The simulated maximum SNDR is 40 dB for a 3.84 MHz bandwidth, which corresponds to a resolution of 6 bits.
    Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on; 01/2009
  • Chi-Wai Leng · Chun-Hung Yang · Chien-Hung Tsai ·
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    ABSTRACT: Based on digital controllers offering significant advantages in DC-DC converters, this paper proposes a digital PWM controller for single-inductor dual-output (SIDO) switching converter operating in discontinuous-conduction mode (DCM). By adopting time-multiplexing (TM) scheme, this converter provides two independent supply voltages using only one inductor, which is suitable for portable devices and system-on-chip (SoC) integration. All design issues of each block including analog-to-digital converter (ADC), digital compensator and digital pulse width modulator (DPWM) are discussed. To save chip area, single look-up table based compensator and modified hybrid DPWM are developed. Simulation results are shown to verify the validity of the proposed work.
  • Chi-Wai Leng · Chun-Hung Yang · Chien-Hung Tsai ·
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    ABSTRACT: Despite significant advantages over analog counterparts, digital controllers for switching DC-DC converters demand the use of different tools such as MATLAB/SIMULINK and Verilog-AMS to model and simulate the design. As a consequence, this inevitably complicates the design procedure. A novel approach is therefore proposed to simplify the process. By using the GUI-based tool developed, the controller for digitally controlled buck converter can be automatically designed and implemented with Verilog HDL under a unique and consistent MATLAB/SIMULINK environment. Verification results of both system-level and mixed-level models are given to show the validity of the proposed design approach.
    Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on; 06/2008