Chiu-Hsien Chan

University of Southern California, Los Angeles, CA, United States

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Publications (7)0 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: A micropower, low-noise, bandpass amplifier for biomedical implants is presented. Operating at low frequency, the amplifier is fully integrated without any external passive components. Low-frequency noise and offset is reduced through the autozeroing technique. The autozeroing frequency and noise bandwidth is optimized to reduce noise folding. The design consists of a novel variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. Subthreshold operation is utilized in all input pair transistors to reduce power consumption, while a low-Gm OTA (operational transconductance amplifier) is realized with a current division technique. A cross-couple parallel pair of source degeneration transistors is utilized to increase the linearity crucial to neural spike detection. The design is realized in a CMOS 0.18mum process. It has an offset of 600muV, a variable gain from 42dB to 0dB, and 50 to 900Hz bandwidth while occupying 0.245mm<sup>2</sup> area. The total circuit consumes only 26muW in a 1.8V power supply; the input referred noise is estimated to be 5.6muV<sub>rms</sub>.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: A micropower, low-noise, bandpass amplifier for biomedical implants is presented. Operating at low frequency, the amplifier is fully integrated without any external passive components. Low-frequency noise and offset is reduced through the autozeroing technique. The autozeroing frequency and noise bandwidth is optimized to reduce noise folding. The design consists of a novel variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. Subthreshold operation is utilized in all input pair transistors to reduce power consumption, while a low-Gm OTA (operational transconductance amplifier) is realized with a current division technique. A cross-couple parallel pair of source degeneration transistors is utilized to increase the linearity crucial to neural spike detection. The design is realized in a CMOS 0.18mum process. It has an offset of 600muV, a variable gain from 42dB to 0dB, and 50 to 900Hz bandwidth while occupying 0.245mm2 area. The total circuit consumes only 26muW in a 1.8V power supply; the input referred noise is estimated to be 5.6muVrms.
    01/2007;
  • International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA; 01/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DGrarrVLSIrarrCA1 reproduces that observed experimentally in the biological DGrarrCA3rarrCA1 circuit
    Engineering in Medicine and Biology Society, 2006. EMBS '06. 28th Annual International Conference of the IEEE; 10/2006
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    [Show abstract] [Hide abstract]
    ABSTRACT: We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.
    Conference proceedings: ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Conference 02/2006; 1:4396-9.
  • [Show abstract] [Hide abstract]
    ABSTRACT: A novel architecture to realize a low-power, low-noise amplifier for cortical neural prostheses is presented. The design consists of a low-noise variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. Discrete-time autozeroing is utilized to reduce the offset and noise. The bandwidth and autozeroing frequency of the amplifier is optimized to reduce noise folding. A current division technique is utilized to achieve a low-Gm OTA (Operational Transconductance Amplifier) so that low frequency operation is realized without any external capacitors. All the input pair transistors are biased in sub-threshold operation to reduce power consumption. A cross-couple parallel pair of source degeneration transistors is employed to increase the linearity crucial to neural spike detection. This design achieves variable gain from 470 (55 dB) to 1. In a CMOS 0.18 um process with 1.8 V power supply, the total circuit occupies 0.245 mm<sup>2</sup> with 26 uW power consumption and 1.8 kHz bandwidth. Total harmonic distortion is less than 1%, while input noise is 4.24 uV<sub>rms</sub> within the band of interest.
    Biomedical Circuits and Systems Conference, 2006. BioCAS 2006. IEEE; 01/2006
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    ABSTRACT: A novel algorithm for population spike (PS) amplitude extraction suitable for real time hardware processing was developed. The extraction method was implemented digitally and experimentally tested on a field programmable gate array (FPGA) device using 16-bit quantization. The accuracy of the implementation was tested using PS signals recorded from hippocampal slices. The PS response of the dentate gyrus granule cells were generated in a multi-electrode array (MEA) setup. Spike amplitudes extracted in real time by the hardware were compared with values resulting from floating-point computation in software. Results showed successful implementation of hardware algorithm with average normalized mean square error (NMSE) less than 2%.
    Biomedical Circuits and Systems, 2004 IEEE International Workshop on; 01/2005