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ABSTRACT: The analytic potential model for symmetric double gate MOSFETs is verified and calibrated with experimental nand p-channel FinFET data over a wide range of gate lengths and bias regions. Quantum mechanical effects are incorporated in the model to reproduce the measured C-V characteristics. The long-channel mobility consists of both a phonon scattering term and a Coulomb scattering term with opposite field dependence. There is a slight mobility dependence on gate length due to the different strain effects in n-and p-channel FinFETs. The 2-D short-channel model has been validated in terms of the measured drain-induced barrier lowering (DIBL), threshold voltage rolloff, and subthreshold current slope of sub-100-nm nand p-channel FinFETs.
IEEE Transactions on Electron Devices 07/2010; · 2.32 Impact Factor
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ABSTRACT: Quantum effects have been incorporated in the analytic potential model for double-gate MOSFETs. From extensive solutions to the coupled Schrodinger and Poisson equations, threshold voltage shift and inversion layer capacitance are extracted as closed form functions of silicon thickness and inversion charge density. With these modifications, the compact model is shown to reproduce C–V and I–V curves of double-gate MOSFETs consistent with those obtained from those measured from experimental FinFET hardware.
Microelectronics Journal. 01/2010;
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ABSTRACT: This brief presents an analytical solution of the electrostatic potential for nanowire MOSFETs in the subthreshold region by solving Poisson's equation in two dimensions (2D) in both semiconductor and gate insulator regions under cylindrical coordinates. Combining the analytical solution with the current continuity equation, one can derive an expression for the subthreshold current, from which the important parameters for short-channel effects (SCEs), such as threshold voltage rolloff, drain-induced barrier lowering, and subthreshold slope degradation, are analytically extracted. The 2D analytical model for SCEs has been validated by the numerical simulation results.
IEEE Transactions on Electron Devices 11/2009; · 2.32 Impact Factor
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ABSTRACT: This paper reviews recent development on compact modeling of multiple-gate (MG) MOSFETs. Long-channel core models based on the analytical potential solutions of Poisson and current continuity equations for symmetric double-gate (DG) and surrounding-gate (SG) MOSFETs have been developed first. Highly accurate explicit solutions are subsequently developed to deal with the implicit algebraic equations of the models. By adding quantum mechanical effects and short-channel effects, as well as capacitance formulations, the core model for DG MOSFETs has been expanded into a full-blown compact model which has been calibrated to and validated by experimental FinFET hardware. With regard to the various other types of MG MOSFETs developed, the core models for DG and SG MOSFETs have been generalized to the less symmetric structures, including quadruple-gate (QG), triple-gate (TG), ??-gate, and ??-gate MOSFETs. Other research activities on multiple-gate MOSFETs are briefly summarized at the end.
Circuits and Systems I: Regular Papers, IEEE Transactions on 09/2009; · 1.97 Impact Factor
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ABSTRACT: This brief reports the experimentally measured strain effect on electron and hole transport in (110)-oriented FinFETs. To separate out the series-resistance component, the low drain-bias resistance is differentiated with respect to the gate voltage. It is found that the hole mobility is enhanced while the electron mobility reduced toward short-channel devices. This effect is attributed to the gate-length-dependent strain in FinFET device structures.
IEEE Transactions on Electron Devices 04/2009; · 2.32 Impact Factor
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ABSTRACT: This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.
IEEE Transactions on Electron Devices 12/2008; · 2.32 Impact Factor
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ABSTRACT: This paper reviews recent development on compact modeling of multiple-gate MOSFETs. Starting with a core model based on the analytic potential solutions for the highly symmetric double-gate (DG) and surrounding-gate (SG) MOSFETs, an explicit solution to the implicit algebraic equations with high accuracy has been developed. With the addition of quantum, short-channel effects, and capacitance formulations, the core model for DG MOSFETs has been expanded into a full-blown compact model which has subsequently been calibrated and validated by FinFET hardware. In view of the various types of experimental multiple-gate MOSFETs developed, the DG and SG MOSFET models have been generalized to other less symmetric structures, including quadruple-gate, triple-gate, Omega-gate, and Pi-gate devices. Finally, research activities in other groups on multiple-gate MOSFETs are briefly summarized.
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE; 10/2008
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ABSTRACT: This paper presents a systematic study of the body doping effect on symmetric double-gate (DG) MOSFETs. Two-dimensional simulation tools are used to investigate the doping effect on long-channel and short-channel devices. Both n-type and p-type doping are studied. For long-channel devices, the threshold voltage shift due to body doping is proportional to the total dopant when the device is fully depleted. Thus, it is straightforward to include the doping effect in compact models. When the device is partially depleted, in addition to the threshold voltage shift, the subthreshold slope can be degraded. For short-channel devices, improvement of the short-channel effects is observed when the body doping concentration is close to the level that makes the device partially depleted.
Semiconductor Science and Technology 12/2007; 23(1):015006. · 1.72 Impact Factor
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ABSTRACT: Explicit continuous models for both double-gate (DG) and surrounding-gate (SG) MOSFETs are presented. These models evolve from previous DG and SG MOSFETs models, which need to solve implicit equations for intermediate parameters by numerical iteration or the table lookup method. By developing approximate explicit solutions for the intermediate parameters, we can express the drain current, terminal charge, transconductance, and transcapacitance as explicit functions of applied voltages as well as the structural parameters. High accuracy and efficiency, combined with inherited favorable features from the previous models, make these new models suitable for circuit simulation programs.
IEEE Transactions on Electron Devices 11/2007; · 2.32 Impact Factor
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ABSTRACT: An analytic potential DG model with quantum mechanical and short channel effects is calibrated to experimental n-channel FinFET data. All C-V and I-V curves from L=10 mum to 50 nm are in excellent agreement with a single mobility model. There is evidence suggesting higher than expected currents from very short fins possibly due to strain enhanced transport effects.
SOI Conference, 2007 IEEE International; 11/2007
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ABSTRACT: This paper presents an analytic charge model for surrounding-gate MOSFETs. Without the charge sheet approximation, the model is based on closed-form solution of Poisson's equation, current continuity equation, and Ward-Dutton linear charge partition. It continuously covers all the operation regions, i.e., linear, saturation, and subthreshold, with unique analytic expressions. The physics-based nature makes this model free of fitting parameters and hence predictive. In addition, it is inherently not source-referenced to avoid asymmetries. It is shown that the current-voltage characteristics generated by this model agree with the numerical simulation results
IEEE Transactions on Electron Devices 04/2007; · 2.32 Impact Factor
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ABSTRACT: This brief investigates the effect of gate overlap and source/drain (S/D) doping gradient on the switching delay of prospective 10-nm CMOS digital circuits. A two-dimensional mixed-mode simulation is used to extract switching delays, taking both the resistance (series) and capacitance (overlap) effects into account. It is shown that for abrupt S/D profiles, optimum performance is obtained at a gate overlap of about 1 nm/edge, depending on the capacitive loading. Underlap is undesirable due to current degradation from the ungated region. It is further shown that a graded S/D doping profile degrades the switching performance. For the same OFF current, a doping gradient les 3 nm/dec is required to avoid significant degradation of switching delays under optimum gate overlap conditions
IEEE Transactions on Electron Devices 01/2007; · 2.32 Impact Factor
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ABSTRACT: In this paper, we assess the potential for bulk CMOS, SOI CMOS, and double-gate CMOS to extend scaling to 10 nm channel length. In addition to the required replacement of silicon dioxide and polysilicon gates by high-k insulator and metal gates for all device types, specific technology requirements are discussed for each device type. 10 nm bulk CMOS requires abrupt placement of n- and p-type dopants at >10<sup>19 </sup> cm<sup>-3</sup> levels for both the channel and the source-drain regions. 10 nm SOI CMOS requires the silicon film thickness to be scaled to its quantum limit of 2 nm. The silicon film thickness requirement is somewhat relaxed in a double-gate device structure. But the self-alignment requirement of a double-gate (or multi-gate) device makes it very challenging to realize a manufacturable process
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on; 11/2006
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ABSTRACT: This paper presents an analytic potential model for long-channel symmetric and asymmetric double-gate (DG) MOSFETs. The model is derived rigorously from the exact solution to Poisson's and current continuity equation without the charge-sheet approximation. By preserving the proper physics, volume inversion in the subthreshold region is well accounted for in the model. The resulting analytic expressions of the drain-current, terminal charges, and capacitances for long-channel DG MOSFETs are continuous in all operation regions, i.e., linear, saturation, and subthreshold, making it suitable for compact modeling. As no fitting parameters are invoked throughout the derivation, the model is physical and predictive. All parameter formulas are validated by two-dimensional numerical simulations with excellent agreement. The model has been implemented in Simulation Program with Integrated Circuit Emphasis version 3 (SPICE3), and the feasibility is demonstrated by the transient analysis of sample CMOS circuits.
IEEE Transactions on Electron Devices 06/2006; · 2.32 Impact Factor
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ABSTRACT: In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L<sub>min</sub>≈4.5(t<sub>Si</sub>+(ε<sub>Si</sub>/ε<sub>I</sub>)t<sub>I</sub>), where t<sub>Si</sub> is the silicon thickness, and ε<sub>I</sub> and t<sub>I</sub> are the permittivity and thickness of the gate insulator. With t<sub>Si</sub> limited to ≥ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L<sub>min</sub>=20 nm is projected for oxides, and L<sub>min</sub>=10 nm for high-κ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.
IEEE Transactions on Electron Devices 06/2006; · 2.32 Impact Factor
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ABSTRACT: A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.
IEEE Transactions on Electron Devices 10/2004; · 2.32 Impact Factor
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ABSTRACT: This letter presents a continuous analytic current-voltage (I-V) model for double-gate (DG) MOSFETs. It is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation. The entire I<sub>ds</sub>(V<sub>g</sub>,V<sub>ds</sub>) characteristics for all regions of MOSFET operation: linear, saturation, and subthreshold, are covered under one continuous function, making it ideally suited for compact modeling. By preserving the proper physics, this model readily depicts "volume inversion" in symmetric DG MOSFETs-a distinctively noncharge-sheet phenomenon that cannot be reproduced by standard charge-sheet based I-V models. It is shown that the I-V curves generated by the analytic model are in complete agreement with two-dimensional numerical simulation results for all ranges of gate and drain voltages.
IEEE Electron Device Letters 03/2004; · 2.85 Impact Factor
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ABSTRACT: This paper presents a unified analytical charge model for long channel symmetric double-gate (DG) and surrounding-gate (SGT) MOSFETs. The proposed analytical charge model continuously covers all the operation regions and achieves both computation efficiency and high accuracy. Unified intrinsic capacitance model for both DG and SGT MOSFETs is also presented for AC simulation. A detailed comparison between the analytical model and numerical solution is conducted to demonstrate the accuracy of the model.
Solid-State Electronics.
