G. Baccarani

University of Bologna, Bolonia, Emilia-Romagna, Italy

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Publications (224)190.31 Total impact

  • Source
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    ABSTRACT: We study a possible circuit solution to overcome the problem of low voltage gain of short-channel graphene FETs. The circuit consists of a fully differential amplifier with a load made of a cross-coupled transistor pair. Starting from the device characteristics obtained from self-consistent ballistic quantum transport simulations, we explore the circuit parameter space and evaluate the amplifier performance in terms of dc voltage gain and voltage gain bandwidth. We show that the dc gain can be effectively improved by the negative differential resistance provided by the cross-coupled pair. Contact resistance is the main obstacle to achieving gain bandwidth products in the terahertz range. Limitations of the proposed amplifier are identified with its poor linearity and relatively large Miller capacitance.
    Solid-State Electronics. 01/2014; 100.
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    ABSTRACT: This paper investigates feasible inverter configurations based on co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same ${rm InAs}/{rm Al}_{0.05}{rm Ga}_{0.95}{rm Sb}$ platform. Based on 3-D full-quantum simulations, the considered devices feature steep subthreshold slopes and relatively high on- currents and are combined into two inverter designs. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights potential of the proposed TFET implementations to perform up to $10times$ and $100times$ faster in low operating power and low standby power environments, respectively. The comparison is conducted at low supply voltages $(V_{rm DD}=0.25~{rm V})$ and for equal levels of static power consumption. The proposed TFET-based platform is thus expected to be a good candidate for low-voltage/low-power applications in near-future technology generations.
    IEEE Transactions on Electron Devices 01/2014; 61(2):473-478. · 2.06 Impact Factor
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    ABSTRACT: The effect of non-parabolic energy-bands on the electrical properties of an In0.53Ga0.47As/In0.52Al0.48As superlattice FET has been investigated. An energy dependent effective mass was fitted on k · p simulation results and the new band model was implemented into a self-consistent Schrödinger–Poisson solver. This analysis has shown that non-parabolicity effects lead to noticeable changes of the device characteristics with respect the parabolic band model, namely: an increase of the on-state current and a steeper transition from the off- to the on-state sustained across several decades of current, at the expense of an increased off-state leakage. Moreover, the larger density of states in the non-parabolic model causes a 47% growth of the output conductance at low VDS, as well as an increased drain conductance in saturation.
    Solid-State Electronics. 01/2014;
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    ABSTRACT: In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply VDD=0.4V are compared with the ITRS specs projected to year 2022. Benchmarking highlights the potential of the proposed ED InGaAs/InAlAs SL-FET to perform up to 1.2× faster than HP specs with 5× lower energy-delay product. This device is thus expected to be a good candidate for the post-CMOS era.
    Solid-State Electronics. 01/2014;
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    ABSTRACT: Design of a suitable technology platform is carried out in this paper for co-integration of simultaneously optimized n- and p-type tunnel field-effect transistors (TFETs). InAs/AlxGa1-xSb heterostructures are considered, and a 3-D full-quantum simulation approach is adopted to investigate the combined effect of Al mole fraction x and transverse quantization on band lineups at the heterojunction. Design optimization leads to a TFET pair with similar dimensions and feasible aspect ratios realized on the same InAs/Al0.05Ga0.95Sb platform. These devices exhibit average subthreshold slopes below 60 mV/dec and relatively high ON-currents of 270 (n-TFET) and 120 μA/μm (p-TFET) at a low-supply voltage VDD=0.4 V. Combined ON- and OFF-state performance of the proposed technology platform is expected to be compatible with low operating power applications, while potential candidates for low standby power scenarios are obtained by reducing TFET cross sections from 10 to 7 nm.
    IEEE Transactions on Electron Devices 01/2014; 61(1):178-185. · 2.06 Impact Factor
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    ABSTRACT: Through self-consistent quantum transport simulations, we evaluate the RF performance of monolayer graphene FETs in the bias region of negative output differential resistance. We show that, compared to the region of quasi-saturation, a voltage gain larger than 10 can be obtained, at the cost of a decrease in the maximum oscillation frequency of about a factor of 3 and the need for a careful circuit stabilization.
    IEEE Transactions on Electron Devices 09/2013; 61(2). · 2.06 Impact Factor
  • E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
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    ABSTRACT: In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the whole channel. So doing, we account for the ambipolar effect, as well as for the tunnel-related leakage current, which becomes appreciable when small band-gap materials are used. The model is validated by comparison with numerical simulation results provided by the k · p technique. With this model we examine the problem of the non-linear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic switching, and design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions.
    Solid-State Electronics 06/2013; 84:96–102. · 1.48 Impact Factor
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    ABSTRACT: A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.
    IEEE Transactions on Electron Devices 04/2013; 60(4):1342-1348. · 2.06 Impact Factor
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    ABSTRACT: In this paper, we present a mode space method for atomistic non-equilibrium Green's function simulations of armchair graphene nanoribbon FETs that includes electron-phonon scattering. With reference to both conventional and tunnel FET structures, we show that, in the ideal case of a smooth electrostatic potential, the modes can be decoupled in different groups without any loss of accuracy. Thus, inter-subband scattering due to electron-phonon interactions is properly accounted for, while the overall simulation time considerably improves with respect to real-space, with a speed-up factor of 40 for a 1.5-nm-wide device. Such factor increases with the square of the device width. We also discuss the accuracy of two commonly used approximations of the scattering self-energies: the neglect of the off-diagonal entries in the mode-space expressions and the neglect of the Hermitian part of the retarded self-energy. While the latter is an acceptable approximation in most bias conditions, the former is somewhat inaccurate when the device is in the off-state and optical phonon scattering is essential in determining the current via band-to-band tunneling. Finally, we show that, in the presence of a disordered potential, a coupled mode space approach is necessary, but the results are still accurate compared to the real-space solution.
    Journal of Applied Physics 02/2013; 113(14). · 2.21 Impact Factor
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    ABSTRACT: A simulation study aimed at investigating the main features in dc and small-signal operating conditions of the hot-electron graphene base transistor (GBT) for analog terahertz operation is presented. Intrinsic silicon is used as reference material. The numerical model is based on a self-consistent Schrödinger-Poisson solution, using a 1-D transport approximation and accounting for multiple-valley and nonparabolicity band effects. Some limitations in the extension of the saturation region and in the output conductance related to the finite quantum capacitance of graphene and to space charge effects are discussed. A small-signal model is developed that catches the essential physics behind the voltage gain and the cutoff frequency, which shows that the graphene quantum capacitance severely limits the former but not the latter. According to simulations carried out within the ballistic transport approximation, a 20-nm-long GBT can achieve at the same time a voltage gain larger than 10 and a cutoff frequency largely above 1 THz within a reasonably wide bias range.
    IEEE Transactions on Electron Devices 01/2013; 60(10):3584-3591. · 2.06 Impact Factor
  • E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
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    ABSTRACT: In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FETs operating under quasi-ballistic conditions. Starting from general expressions of the current–voltage characteristics worked out in a previous paper, we extract the above parameters and their functional dependence on inversion-layer charge and device length. The computation is based on a rigorous analytic solution of the BTE and on a numerical solution of the coupled Schrödinger–Poisson equations, by which multiple subbands are taken into account. We propose three different definitions of the ballistic ratio, clarify their meaning and compute their values against the gate voltage and the device length. As opposed to most phenomenological treatments addressing this subject for 2D nanoscale MOSFETs, the strength of our approach is that the aforementioned parameters can be computed from the knowledge of the scattering probabilities, without introducing any major simplifying assumptions.
    Microelectronics Journal 01/2013; · 0.91 Impact Factor
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    ABSTRACT: Physically based models of hot-carrier stress and dielectric-field-enhanced thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated power devices over an extended range of stress biases and ambient temperatures. An analytical formulation of the distribution function accounting for the effects of the full band structure has been employed for hot-carrier modeling purposes. A quantitative understanding of the kinetics and local distribution of degradation is achieved, and the drift of the most relevant parameters is nicely predicted on an extended range of stress times and biases.
    IEEE Transactions on Electron Devices 01/2013; 60(2):691-698. · 2.06 Impact Factor
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    ABSTRACT: The impact of semiconductor/oxide interface traps (ITs) on the turn-on characteristics of tunnel field-effect transistors (TFETs) is carefully investigated through TCAD. IT density is treated as a 2-D continuum. Both a conventional and an advanced nanowire TFET, designed to fulfill ITRS specs, are addressed. Surprisingly, in conventional TFETs, high concentrations of acceptor-like ITs can suppress device ambipolarity, thus reducing transistor's OFF-state current.
    IEEE Electron Device Letters 01/2013; 34(12):1557-1559. · 2.79 Impact Factor
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    ABSTRACT: For the first time, a simulation study is reported of a device formed by stacking an n+-Si layer (emitter), a monolayer graphene sheet (base), and a second n-Si layer (collector), operating as a graphene-base heterojunction transistor. The device differs from the recently proposed hot-electron graphene-base transistor (GBT), where graphene is sandwiched between the two dielectric layers, in the current flow being regulated mainly by thermionic emission over the potential-energy barrier, rather than by tunneling through the emitter-contact Schottky barrier. The simulations are based on a 1-D quantum transport model with the effective mass approximation and nonparabolic corrections. In addition to being much easier to fabricate compared with the GBT, the device is shown to be able to provide 104 ON/OFF current ratio, current densities well in excess of 0.1 A/μm2 and cutoff frequencies well above 1 THz, together with an intrinsic dc small-signal voltage gain larger than 10. Even though the simulation model is somewhat idealized, since ballistic transport is assumed and Si-graphene interfaces are ideal, our results show that this device is a serious competitor for high-frequency RF applications.
    IEEE Transactions on Electron Devices 01/2013; 60(12):4263-4268. · 2.06 Impact Factor
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    ABSTRACT: A new TCAD-based approach is used to investigate hot-carrier stress (HCS) effects, especially suited for power devices. Physically-based degradation models are used to determine the interface trap generation at different stress biases and ambient temperatures. Special attention has been given to the high current-voltage regimes, when significant self-heating effects and impact ionization play a relevant role. By monitoring the linear and saturation regimes of a rugged LDMOS at different stress biases and times, the spatial and energetic distribution of acceptor- and donor-type traps has been investigated for the first time confirming the experimental results.
    Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on; 01/2013
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    ABSTRACT: Tunnel FETs (TFETs) are promising alternatives to the conventional CMOS technology for steeper-than-60mV/dec subthreshold slopes (SS) required to limit power consumption of integrated circuits [1]. Current challenges for TFET integration into practical circuit applications include reaching acceptable ION levels, suppressing ambipolar effects, improving output characteristics [2], and simultaneously co-integrating optimized n-and p-type devices. All of these issues are carefully taken into account in this work. Device- and circuit-level design of TFET inverters is proposed, based on co-optimized n-and p-type TFETs integrated on the same InAs/ Al0.05Ga0.95Sb platform. A full-band quantum simulation approach is adopted to properly account for quantum effects which strongly influence TFET device, and hence circuit, performance. This advances the state of the art of TFET-based circuit literature, which is mostly based on simplified TCAD models [3], with rare calibrations against atomistic calculations [41.
    Energy Efficient Electronic Systems (E3S), 2013 Third Berkeley Symposium on; 01/2013
  • Source
    Roberto Grassi, Tony Low, Antonio Gnudi, Giorgio Baccarani
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    ABSTRACT: In this work, we clarify the physical mechanism for the phenomenon of negative output differential resistance (NDR) in short-channel graphene FETs (GFETs) through non-equilibrium Green's function (NEGF) simulations and a simpler semianalytical ballistic model that captures the essential physics. This NDR phenomenon is due to a transport mode bottleneck effect induced by the graphene Dirac point in the different device regions, including the contacts. NDR is found to occur only when the gate biasing produces an n-p-n or p-n-p polarity configuration along the channel, for both positive and negative drain-source voltage sweep. In addition, we also explore the impact on the NDR effect of contact-induced energy broadening in the source and drain regions and a finite contact resistance.
    IEEE Transactions on Electron Devices 08/2012; 60(1). · 2.06 Impact Factor
  • R. Grassi, T. Low, A. Gnudi, G. Baccarani
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    ABSTRACT: We discuss the phenomenon of negative output differential resistance of short-channel graphene FETs at room temperature, whose physical origin arises from a transport-mode bottleneck induced by the contact-doped graphene. We outline a simple semianalytical model, based on semiclassical ballistic transport, which captures this effect and qualitatively reproduces results from the non-equilibrium Green's function approach (NEGF). We find that this effect is robust against phonon scattering.
    Device Research Conference (DRC), 2012 70th Annual; 01/2012
  • E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
    [Show abstract] [Hide abstract]
    ABSTRACT: In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the whole channel. So doing, we account for the ambipolar effect, as well as for the tunnel-related leakage current, which becomes appreciable when small band-gap materials are used. The model is validated by comparison with numerical simulation results provided by the kp technique.
    Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on; 01/2012
  • E. Gnani, S. Reggiani, A. Gnudi, G. Baccarani
    [Show abstract] [Hide abstract]
    ABSTRACT: In this work we examine the problem of the nonlinear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic operation and severely degrades the device dynamic properties compared with standard CMOS FETs. The problem is investigated with the help of an analytical model which highlights the constraints of the device design by splitting the effects of the tunneling probability from the density of states in the source, channel and drain, and makes it possible to design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions. So doing, we remove the above characteristics' feature and recover a large drain conductance without degrading the subthreshold slope. The optimized device is numerically simulated using the k·p model, whose results are in fair agreement with the analytical one.
    Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European; 01/2012

Publication Stats

2k Citations
190.31 Total Impact Points

Institutions

  • 1976–2014
    • University of Bologna
      • • The Advanced Research Center on Electronic Systems for Information and Communication Technologies "E. De Castro" ARCES
      • • "Guglielmo Marconi" Department of Electrical, Electronic and Information Engineering DEI
      • • School of Engineering and Architecture
      Bolonia, Emilia-Romagna, Italy
  • 2009
    • University of Udine
      Udine, Friuli Venezia Giulia, Italy
  • 1997
    • Università degli Studi di Trento
      • Department of Mathematics
      Trento, Trentino-Alto Adige, Italy
  • 1993–1994
    • NEC Corporation
      Edo, Tōkyō, Japan
  • 1992
    • Technische Universität Hamburg-Harburg
      Hamburg, Hamburg, Germany