G. Baccarani

University of Bologna, Bolonia, Emilia-Romagna, Italy

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Publications (235)231.31 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. In this review, the electrical characteristics of the STI-based LDMOS transistors are investigated over an extended range of operating conditions through experiments and numerical analysis. The LDMOS high electric-field characteristics are explained to the purpose of investigating the effects on reliability and device performance under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to provide an understanding of the degradation kinetics and mechanisms. TCAD simulations of the degradation are finally proposed to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.
    Solid-State Electronics 12/2014; 102. · 1.51 Impact Factor
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    ABSTRACT: In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply VDD=0.4V are compared with the ITRS specs projected to year 2022. Benchmarking highlights the potential of the proposed ED InGaAs/InAlAs SL-FET to perform up to 1.2× faster than HP specs with 5× lower energy-delay product. This device is thus expected to be a good candidate for the post-CMOS era.
    Solid-State Electronics 11/2014; · 1.51 Impact Factor
  • ESSDERC 2014; 09/2014
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    ABSTRACT: We develop a semianalytical model for monolayer graphene field-effect transistors in the ballistic limit. Two types of devices are considered: in the first device, the source and drain regions are doped by charge transfer with Schottky contacts, while, in the second device, the source and drain regions are doped electrostatically by a back gate. The model captures two important effects that influence the operation of both devices: (i) the finite density of states in the source and drain regions, which limits the number of states available for transport and can be responsible for negative output differential resistance effects, and (ii) quantum tunneling across the potential steps at the source-channel and drain-channel interfaces. By comparison with a self-consistent non-equilibrium Green's function solver, we show that our model provides very accurate results for both types of devices, in the bias region of quasi-saturation as well as in that of negative differential resistance.
    Journal of Applied Physics 09/2014; 116(11):114505-114505-9. · 2.19 Impact Factor
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    ABSTRACT: The effect of non-parabolic energy-bands on the electrical properties of an In0.53Ga0.47As/In0.52Al0.48As superlattice FET has been investigated. An energy dependent effective mass was fitted on k · p simulation results and the new band model was implemented into a self-consistent Schrödinger–Poisson solver. This analysis has shown that non-parabolicity effects lead to noticeable changes of the device characteristics with respect the parabolic band model, namely: an increase of the on-state current and a steeper transition from the off- to the on-state sustained across several decades of current, at the expense of an increased off-state leakage. Moreover, the larger density of states in the non-parabolic model causes a 47% growth of the output conductance at low VDS, as well as an increased drain conductance in saturation.
    Solid-State Electronics 08/2014; · 1.51 Impact Factor
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    ABSTRACT: The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shallow-trench isolation (STI) has been investigated through experiments and TCAD predictions under AC pulsed stress conditions. The systematic increase of degradation with frequency and the dependence on rise/fall times and duty cycle has been explained by using a new TCAD approach based on physical models. The degradation increase can be correlated to the peak of the HCS reaction rate at the rising edge. The analysis carried out on two different devices confirms the TCAD predictions.
    2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD); 06/2014
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    ABSTRACT: We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Tunnel Field-Effect Transistor (TFET) nanowires. It will be shown that the gate-drain capacitance follows the same trend as the total gate capacitance (but with smaller values) over the whole Vgs range, hence confirming the capacitance estimation provided by semiclassical TCAD tools from a qualitative point of view. However, we find that the gate capacitance exhibits a nonmonotonic behavior as a function of the gate voltage, with plateaus and bumps, depending on the amount of energy quantization determined by the device cross-sectional size, and the position of channel-conduction subbands relative to the Fermi level in the drain contact. From this point of view, semiclassical TCAD tools seem to be inaccurate for capacitance estimation in aggressively scaled TFET devices.
    2014 15th International Conference on Ultimate Integration on Silicon (ULIS); 04/2014
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    ABSTRACT: A novel approach to optimize tunnel field-effect transistors (TFETs) by technology computer-aided design simulations is reported. The most interesting outcome of our design effort is a dual-metal-gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly < 60 mV/decade over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain-current decade or more. The DMG-TFET simultaneously fulfills both the low-standby-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors.
    IEEE Transactions on Electron Devices 03/2014; PP(99):1-1. · 2.36 Impact Factor
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    ABSTRACT: This paper investigates feasible inverter configurations based on co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same ${rm InAs}/{rm Al}_{0.05}{rm Ga}_{0.95}{rm Sb}$ platform. Based on 3-D full-quantum simulations, the considered devices feature steep subthreshold slopes and relatively high on- currents and are combined into two inverter designs. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights potential of the proposed TFET implementations to perform up to $10times$ and $100times$ faster in low operating power and low standby power environments, respectively. The comparison is conducted at low supply voltages $(V_{rm DD}=0.25~{rm V})$ and for equal levels of static power consumption. The proposed TFET-based platform is thus expected to be a good candidate for low-voltage/low-power applications in near-future technology generations.
    IEEE Transactions on Electron Devices 02/2014; 61(2):473-478. · 2.36 Impact Factor
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    ABSTRACT: We study a possible circuit solution to overcome the problem of low voltage gain of short-channel graphene FETs. The circuit consists of a fully differential amplifier with a load made of a cross-coupled transistor pair. Starting from the device characteristics obtained from self-consistent ballistic quantum transport simulations, we explore the circuit parameter space and evaluate the amplifier performance in terms of dc voltage gain and voltage gain bandwidth. We show that the dc gain can be effectively improved by the negative differential resistance provided by the cross-coupled pair. Contact resistance is the main obstacle to achieving gain bandwidth products in the terahertz range. Limitations of the proposed amplifier are identified with its poor linearity and relatively large Miller capacitance.
    Solid-State Electronics 01/2014; 100. · 1.51 Impact Factor
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    ABSTRACT: Design of a suitable technology platform is carried out in this paper for co-integration of simultaneously optimized n- and p-type tunnel field-effect transistors (TFETs). InAs/AlxGa1-xSb heterostructures are considered, and a 3-D full-quantum simulation approach is adopted to investigate the combined effect of Al mole fraction x and transverse quantization on band lineups at the heterojunction. Design optimization leads to a TFET pair with similar dimensions and feasible aspect ratios realized on the same InAs/Al0.05Ga0.95Sb platform. These devices exhibit average subthreshold slopes below 60 mV/dec and relatively high ON-currents of 270 (n-TFET) and 120 μA/μm (p-TFET) at a low-supply voltage VDD=0.4 V. Combined ON- and OFF-state performance of the proposed technology platform is expected to be compatible with low operating power applications, while potential candidates for low standby power scenarios are obtained by reducing TFET cross sections from 10 to 7 nm.
    IEEE Transactions on Electron Devices 01/2014; 61(1):178-185. · 2.36 Impact Factor
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    ABSTRACT: The impact of semiconductor/oxide interface traps (ITs) on the turn-on characteristics of tunnel field-effect transistors (TFETs) is carefully investigated through TCAD. IT density is treated as a 2-D continuum. Both a conventional and an advanced nanowire TFET, designed to fulfill ITRS specs, are addressed. Surprisingly, in conventional TFETs, high concentrations of acceptor-like ITs can suppress device ambipolarity, thus reducing transistor's OFF-state current.
    IEEE Electron Device Letters 12/2013; 34(12):1557-1559. · 3.02 Impact Factor
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    ABSTRACT: For the first time, a simulation study is reported of a device formed by stacking an n+-Si layer (emitter), a monolayer graphene sheet (base), and a second n-Si layer (collector), operating as a graphene-base heterojunction transistor. The device differs from the recently proposed hot-electron graphene-base transistor (GBT), where graphene is sandwiched between the two dielectric layers, in the current flow being regulated mainly by thermionic emission over the potential-energy barrier, rather than by tunneling through the emitter-contact Schottky barrier. The simulations are based on a 1-D quantum transport model with the effective mass approximation and nonparabolic corrections. In addition to being much easier to fabricate compared with the GBT, the device is shown to be able to provide 104 ON/OFF current ratio, current densities well in excess of 0.1 A/μm2 and cutoff frequencies well above 1 THz, together with an intrinsic dc small-signal voltage gain larger than 10. Even though the simulation model is somewhat idealized, since ballistic transport is assumed and Si-graphene interfaces are ideal, our results show that this device is a serious competitor for high-frequency RF applications.
    IEEE Transactions on Electron Devices 12/2013; 60(12):4263-4268. · 2.36 Impact Factor
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    ABSTRACT: A simulation study aimed at investigating the main features in dc and small-signal operating conditions of the hot-electron graphene base transistor (GBT) for analog terahertz operation is presented. Intrinsic silicon is used as reference material. The numerical model is based on a self-consistent Schrödinger-Poisson solution, using a 1-D transport approximation and accounting for multiple-valley and nonparabolicity band effects. Some limitations in the extension of the saturation region and in the output conductance related to the finite quantum capacitance of graphene and to space charge effects are discussed. A small-signal model is developed that catches the essential physics behind the voltage gain and the cutoff frequency, which shows that the graphene quantum capacitance severely limits the former but not the latter. According to simulations carried out within the ballistic transport approximation, a 20-nm-long GBT can achieve at the same time a voltage gain larger than 10 and a cutoff frequency largely above 1 THz within a reasonably wide bias range.
    IEEE Transactions on Electron Devices 10/2013; 60(10):3584-3591. · 2.36 Impact Factor
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    ABSTRACT: The working principles of the hot-electron graphene base transistor (GBT) for analog terahertz operation have been investigated by means of a self-consistent Schrodinger-Polsson solver code. Its regions of operation are defined and discussed. With the help of a small-signal model, it is shown that the cutoff frequency does not depend on the quantum capacitance of the graphene layer, which on the contrary severely affects the intrinsic voltage gain, and that terahertz operation is possible.
    ESSDERC 2013; 09/2013
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    ABSTRACT: Through self-consistent quantum transport simulations, we evaluate the RF performance of monolayer graphene FETs in the bias region of negative output differential resistance. We show that, compared to the region of quasi-saturation, a voltage gain larger than 10 can be obtained, at the cost of a decrease in the maximum oscillation frequency of about a factor of 3 and the need for a careful circuit stabilization.
    IEEE Transactions on Electron Devices 09/2013; 61(2). · 2.36 Impact Factor
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    ABSTRACT: Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.
    ESSDERC 2013 - 43rd European Solid State Device Research Conference; 09/2013
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    ABSTRACT: Power device reliability is one of the key challenges of next generation Smart-Power technologies. As a consequence, device performance needs to be optimized accounting for hot-carrier stress degradation issues. To this purpose, numerical simulation tools are commonly used, but the TCAD modeling of performance drifts due to electrical stress is still an open issue. Physics-based analytical models and TCAD based approaches have been proposed and devised for the investigation of the parameter degradation in the linear transport regime and its localization in STI-based LDMOS devices. A thorough investigation of the degradation under high-gate stress biases, corresponding to impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependence of the parameter drifts.
    ESSDERC 2013 - 43rd European Solid State Device Research Conference; 09/2013
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    ABSTRACT: In this work the effect of high-k gate dielectrics on the power-speed performance of SL-FETs realized with the InGaAs/InAlAs and InGaAs/InP material pairs is investigated by numerical simulations. The analysis shows that the InGaAs/InP pair, in association with Al2O3 as the gate dielectric, provides the most promising results for high-performance applications, i.e. an on-state current approaching 2 mA/μm and an intrinsic delay lower than 0.16 ps at a supply voltage of 0.4 V. The average subthreshold swing SS is much lower than 60 mV/dec over six current decades and the point slope SS ≈ 20mV/dec. These results outperform the ITRS requirements projected to year 2022 in terms of both static and dynamic power dissipation, and make the proposed device well suited for high-performance and low-power applications at the same time.
    ESSDERC 2013 - 43rd European Solid State Device Research Conference; 09/2013
  • E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
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    ABSTRACT: In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the whole channel. So doing, we account for the ambipolar effect, as well as for the tunnel-related leakage current, which becomes appreciable when small band-gap materials are used. The model is validated by comparison with numerical simulation results provided by the k · p technique. With this model we examine the problem of the non-linear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic switching, and design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions.
    Solid-State Electronics 06/2013; 84:96–102. · 1.51 Impact Factor

Publication Stats

2k Citations
231.31 Total Impact Points

Institutions

  • 1976–2014
    • University of Bologna
      • • The Advanced Research Center on Electronic Systems for Information and Communication Technologies "E. De Castro" ARCES
      • • "Guglielmo Marconi" Department of Electrical, Electronic and Information Engineering DEI
      • • School of Engineering and Architecture
      Bolonia, Emilia-Romagna, Italy
  • 2009
    • University of Udine
      Udine, Friuli Venezia Giulia, Italy
  • 1997
    • Università degli Studi di Trento
      • Department of Mathematics
      Trento, Trentino-Alto Adige, Italy
  • 1993–1994
    • NEC Corporation
      Edo, Tōkyō, Japan
  • 1992
    • Technische Universität Hamburg-Harburg
      Hamburg, Hamburg, Germany