F.K. Baker

Publications (15)22.83 Total impact

• Article: A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

  J.D. Hayden, T.C. Mele, A.H. Perera, D. Burnett, F.W. Walczyk, C.S. Lage, F.K. Baker, M. Woo, W. Paulson, M. Lien, Y.-C. See, D. Denning, S.J. Cosentino
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  ABSTRACT: A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V _ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency ( f _T) of 14 GHz with a collector-emitter breakdown voltage ( BV _CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f _T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process
  IEEE Transactions on Electron Devices 08/1992; · 2.32 Impact Factor
• Article: The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p+-gate p-channel MOSFETs with fluorine incorporation

  Hsing-Huang Tseng, P.J. Tobin, F.K. Baker, J.R. Pfiester, K. Evans, P.L. Fejes
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  ABSTRACT: Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage ( V _TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V _TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO₂/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V _TP shift
  IEEE Transactions on Electron Devices 08/1992; · 2.32 Impact Factor
• Article: An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

  J.R. Pfiester, R.D. Sivan, C.D. Gunderson, N.E. Crain, J.-H. Lin, H.M. Liaw, C.A. Seelbach, F.K. Baker
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  ABSTRACT: An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion
  IEEE Transactions on Electron Devices 12/1991; · 2.32 Impact Factor
• Article: A high-performance half-micrometer generation CMOS technology for fast SRAMs

  J.D. Hayden, F.K. Baker, S.A. Ernst, R.E. Jones, J. Klein, M. Lien, T.F. McNelly, T.C. Mele, H. Mendez, B.-Y. Nguyen, L.C. Parrillo, W. Paulson, J.R. Pfiester, F. Pintchovski, Y.-C. See, R.D. Sivan, B.M. Somero, E.O. Travis
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  ABSTRACT: An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n⁺ to p⁺ space to less than 2 μm and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2-μm active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n⁺/p⁺ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3-μm effective channel length. Transistor design is optimized to reduce the polysilicon gate bird's beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF₂ with B ¹¹ for the p⁺ S/D implant. A titanium salicide process provides strapping between n⁺/p⁺ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K× 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0°C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved
  IEEE Transactions on Electron Devices 05/1991; · 2.32 Impact Factor
• Article: A circuit level hot-carrier evaluation system

  P.G.Y. Tsui, P.M. Lee, F.K. Baker, J.D. Hayden, L. Howington, L. Tiwald, B. Mowry
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  ABSTRACT: A fully integrated system that facilitates the evaluation and prediction of hot-carrier effects at the circuit level is described. The system is capable of executing constant voltage and constant current ratio stress conditions at the transistor level, performing extensive data analysis and extraction, and simulating circuit reliability at a user-defined future time. Through these enhancements, more precise model parameter values can be attained, which in turn improves the overall accuracy of the circuit aging simulation. Quantitative verification of the simulation results against experimental data was accomplished using 0.5-μm CMOS ring oscillators. The reliability of the ring oscillators as a function of stress time, power supply voltage, capacitive loading, and passivation technology is analyzed. In all these cases, less than 2% absolute error was observed between the experimental and simulation results when using this automated hot-carrier evaluation system
  IEEE Journal of Solid-State Circuits 04/1991; · 3.23 Impact Factor
• Article: The effects of boron penetration on p+ polysilicon gated PMOS devices

  J.R. Pfiester, F.K. Baker, T.C. Mele, H.-H. Tseng, P.J. Tobin, J.D. Hayden, J.W. Miller, C.D. Gunderson, L.C. Parrillo
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  ABSTRACT: The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V _FB, increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface
  IEEE Transactions on Electron Devices 09/1990; · 2.32 Impact Factor
• Conference Proceeding: The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF2 implanted P+ gate p-channel MOSFETs

  Hsing-Huang Tseng, P.J. Tobin, F.K. Baker, J.R. Pfiester, K. Evans, P. Fejes
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  ABSTRACT: A study of the effects of P+ poly gate microstructure and gate oxide cycle on boron penetration from gate electrode through thin oxide is reported. The boron diffusion and the trap generation in the oxide can be significantly reduced by using an as-deposited amorphous Si gate and an oxide cycle which incorporates less Cl into the film. A strong interaction between fluorine and boron results in boron penetration into the channel and electron trap generation in the oxide. A larger grain size means fewer grain boundaries are available for boron and fluorine diffusion from the P+ gate to oxide. Less fluorine in the oxide results in less electron trap generation and less boron penetration to the Si substrate. A smaller content of Cl in the oxide results in a reduction of boron penetration. Finally, a co-implant of boron and fluorine into the as-deposited amorphous Si gate results in minimum boron diffusion into the Si substrate, which may provide the control of fluorine dose needed to reduce the interface trap density between oxide/Si interface. Increasing the grain size of the poly gate as reported above can be applied to reduce the large concentration of fluorine introduced into the gate oxide by other processes such as CVD tungsten polycide technology
  VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on; 07/1990
• Article: A physical model for boron penetration through thin gate oxides from p/sup +/ polysilicon gates

  J.R. Pfiester, L.C. Parrillo, F.K. Baker
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  ABSTRACT: Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation.< >
  IEEE Electron Device Letters 07/1990; · 2.85 Impact Factor
• Article: A selectively deposited poly-gate ITLDD process with self-aligned LDD/channel implantation

  J.R. Pfiester, F.K. Baker, R.D. Sivan, N. Crain, J.-H. Lin, M. Liaw, C. Seelbach, C. Gunderson, D. Denning
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  ABSTRACT: An inverse-T lightly doped drain (ITLDD) CMOS process which features improved hot-carrier effects and self-aligned source/drain and channel implantation profiles is presented. Compensation effects by the heavy channel doping on the light N/sup -//P/sup -/ profile are minimized in this ITLDD structure, because the implants are self-aligned to the polysilicon-gate edge. In addition, because selective polysilicon deposition rather than an incomplete poly-gate etchback is used to define the ITLDD structure, a simpler, more manufacturable process is obtained due to improved control of the thin poly-gate shelf thickness.< >
  IEEE Electron Device Letters 07/1990; · 2.85 Impact Factor
• Conference Proceeding: An integrated system for circuit level hot-carrier evaluation

  P.G.Y. Tsui, L. Howington, P.M. Lee, T. Tiwald, B. Mowry, F.K. Baker, J.D. Hayden, B.B. Feaster, B. Garbs
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  ABSTRACT: An integrated system designed to evaluate and predict hot-carrier effects at the circuit level is described. The system will perform device stress, collect data, extract parameters, and simulate circuit aging behavior using the circuit aging simulator from UC Berkeley. Enhancements made to the device-stress and data-analysis portions of the system were found necessary to achieve accurate circuit reliability prediction. Less than 2% error is observed between the measured and simulated performance of a 0.5 μm ring oscillator test circuit
  Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990; 06/1990
• Conference Proceeding: The influence of fluorine on threshold voltage instabilities in p + polysilicon gated p-channel MOSFETs

  F.K. Baker, J.R. Pfiester, T.C. Mele, H.-H. Tseng, P.J. Tobin, J.D. Hayden, C.D. Gunderson, L.C. Parrillo
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  ABSTRACT: It is shown that fluorine plays a major role in the penetration of boron into and through the gate oxides of p-channel MOSFETs that use p ⁺ doped polysilicon gates. Boron penetration results in large positive shifts in V _FB, increased p-channel subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Inclusion of a phosphorus coimplant or TiSi₂ salicide is shown to minimize this effect. The boron penetration phenomenon is modeled by the creation of a very shallow, fully depleted p-type layer in the silicon substrate close to the SiO ₂-Si interface. Elemental boron is shown to be superior to BF ₂ as an implant species for surface channel submicron PMOS devices
  Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International; 01/1990
• Conference Proceeding: A self-aligned LDD/channel implanted ITLDD process with selectively-deposited poly gates for CMOS VLSI

  J.R. Pfiester, F.K. Baker, R.D. Sivan, N. Crain, H.-H. Lin, M. Liaw, C. Seelbach, C. Gunderson, D. Denning
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  ABSTRACT: A novel inverse-T LDD (ITLDD) CMOS process has been developed as part of a submicron CMOS technology that features self-aligned LDD/channel implantation for improved hot-carrier protection. The resulting ITLDD device structures can be designed with very light n- and p-LDD (lightly doped drain) implantations. This leads to lower substrate current due to reduced compensation effects of the lightly doped LDD regions by the heavy channel doping profile. The use of selective polysilicon deposition rather than an incomplete polysilicon etchback process to define the inverse-T gate results in a simpler, more manufacturable process for the ITLDD structure
  Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International; 01/1990
• Article: The influence of tilted source-drain implants on high-field effects in submicrometer MOSFETs

  F.K. Baker, J.R. Pfiester
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  ABSTRACT: Asymmetries in MOSFET high-field effects, such as impact ionization and bipolar snapback, are used to examine the influence of tilted source-drain implants on device reliability. Several process variables, including source-drain implant conditions and anneal time, are varied to determine how they affect these asymmetries. Using two-dimensional process and devices simulations to explain the physical origins of these effects, the lightly doped drain (LDD) structure is shown to offer some immunity to tilt-angle-induced reliability problems. These results are used to suggest guidelines for the design of the LDD structure
  IEEE Transactions on Electron Devices 01/1989; · 2.32 Impact Factor
• Conference Proceeding: Asymmetrical high field effects in submicron MOSFET's

  J.R. Pfiester, F.K. Baker
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  ABSTRACT: Nonzero implantation tilt angles are shown to cause an asymmetry in high-field effects, such as bipolar snapback and hot carrier injection, even when adequate source/drain overlap is achieved. This effect can cause large variations in a MOSFET's reliability, depending on its orientation and location within the wafer. Based on two-dimensional process and device simulations, it is shown that the Lightly Doped Drain (LDD) is more promising than the Graded Source/Drain (GSD) in avoiding these asymmetrical high-field effects at submicron dimensions. Guidelines are presented for the design of an optimized LDD structure, and substrate current is proposed as the best monitor for asymmetries in source/drain profiles.
  Electron Devices Meeting, 1987 International; 02/1987
• Conference Proceeding: A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technology

  L.C. Parrillo, S.J. Cosentino, R.W. Mauntel, B.A. Bergami, P.J. Tobin, F.K. Baker, S. Poon, Y. Yoshii, F. Pintchovski, S.W. Sun, F.T. Liou, J. Alvis, M. Kearney, M. Swensor
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  ABSTRACT: We have developed an advanced CMOS technology for application in fast SRAMS, non-volatile memory, microprocessor and logic circuits. Features of the 1.2µm (gate and contact) double-level-poly, double-level-metal technology include a twin-well CMOS [1] structure in n- or p-type starting material, SILO isolation [2] for high packing density, 250 A thick gate oxide, 0.9µm-nominal-effective channel-length (Leff) NMOS devices with moderately lightly doped drains [3], optional LDD PMOS devices for high-voltage circuit applications, low-temperature-flow BPSG, a TiSi/TiN/Al contact and barrier metallurgy, and three-micron and four-micron first-and second-level-metal pitches respectively. Novel features of the technology include a single-mask dual-chanstop PMOS field-and-punch-through-implant scheme as well as disposable gate-sidewall spacers for LDD formation on CMOS devices. Reliability has been designed into the technology with emphasis on hot-carrier-protected transistors and metallization.
  Electron Devices Meeting, 1986 International; 02/1986