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ABSTRACT: In this paper, an analytical model of intrinsic carbon-nanotube field-effect transistors is presented. The origins of the channel carriers are analyzed in the ballistic limit. A noniterative surface-potential model is developed based on an analytical electrostatic model and a piecewise constant quantum-capacitance model. The model is computationally efficient with no iteration or numerical integration involved, thus facilitating fast circuit simulation and system optimization. Essential physics such as drain-induced barrier lowering and quantum capacitance are captured with reasonable accuracy.
IEEE Transactions on Electron Devices 09/2011; · 2.32 Impact Factor
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ABSTRACT: A compact model is presented which realistically reproduces TFET characteristics and allows complex circuit simulation and parameter optimization studies. The model has been applied to circuit simulations which reveal anomalous switching behavior, and to a multi-parameter optimization study which quantifies the power-performance advantage of the TFET over conventional MOSFETs.
Device Research Conference (DRC), 2011 69th Annual; 07/2011
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ABSTRACT: After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an ~ 8Ã improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.
Proceedings of the IEEE 03/2010; · 6.81 Impact Factor
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ABSTRACT: Because of high carrier velocities and quasi-ballistic transport properties, carbon-based (nanotube, graphene) field effect transistors (CNFETs) are considered to be potential candidates to replace CMOS in future technology generations . Most prior modeling of CNFETs has involved complex models, such as NEGF , but to properly evaluate these devices in circuits and systems, efficient compact models are required. In this paper, a fully analytical model based on ballistic transport and careful analysis of quantum capacitances is developed. This model requires neither iteration nor numeric integration. The model agrees well with numerical simulation and, in the limit of good contacts, predicts that a new effect, source exhaustion (using up all available carriers in the source), should limit the current. The model has also been integrated into a system level design optimization program which evaluates optimal device parameters based on system-level design objectives. The CNFET is projected to achieve 5Ã chip-level speed up over PDSOI at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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ABSTRACT: A simple and efficient model of carbon nanotube field effect transistor (CNFET) is necessary to perform system-level optimization. In this paper, an analytical model with no iteration or integration is developed, including an analytical electrostatic model for the surface potential and simplification of scattering effects. The model is computationally efficient, but includes essential physics such as DIBL effect and scattering.
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European; 10/2008
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ABSTRACT: This paper has described the performance of CMOS and categorises the variability. The inability to scale the tolerance of multiple electrical parameters along with their nominal value has contributed to a virtual crisis in the ability to improve performance and power consumption in new processes. The continued infusion of new materials and structures provide an illusion of conventional scaling, but assert additional idiosyncrasies as well. New device structures and materials may allow CMOS to scale further, but variability isn't likely to decrease, since smaller devices contain fewer atoms and consequently exhibit less self-averaging. The situation may be improved by removing most of the doping.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: We demonstrate over 40% CMOS performance gain with minimal process changes by lowering the operating temperature from 100degC to -50degC. For the same performance, the lower temperature operation delivers a 60% reduction in power-delay product at a reduced supply voltage. Coupled with recent advances in liquid cooling techniques, our results suggest that sub-ambient temperature operation is an attractive option for high performance and energy-efficient CMOS.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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A. W. Topol,
D. C. La Tulipe,
L. Shi, D. J. Frank,
K. Bernstein,
S. E. Steen,
A. Kumar,
G. U. Singco,
A. M. Young,
K. W. Guarini,
M. Ieong
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ABSTRACT: Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers. This process provides the shortest distance between the stacked layers (<2 µm), the highest interconnection density (>10<sup>8</sup> vias/cm<sup>2</sup>), and extremely aggressive wafer-to-wafer alignment (submicron) capability.
Ibm Journal of Research and Development 08/2006; · 0.72 Impact Factor
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ABSTRACT: Since power dissipation is becoming a dominant limitation on the continued improvement of CMOS technology, technologists must understand the best way to design transistors in the presence of power constraints. The primary objective is to obtain as much performance as possible for a fixed amount of power, and it is chip performance, not device performance, that matters. In order to investigate this regime, we have captured in simplified models the basic elements for determining chip performance, including intrinsic transistor characteristics, circuit delay, tolerance issues, basic microprocessor composition, and power dissipation and heat removal considerations. These models have been assembled in a processor-level technology-optimization program to study the characteristics of optimal technology across many generations of CMOS. The results that are presented elucidate the limits of future CMOS technology improvements, the optimal energy consumption conditions, and the relative benefits of various proposed technology enhancements, including high-k gate insulators, metal gates, high-mobility semiconductors, improved heat removal, and the use of multiple layers of circuitry.
Ibm Journal of Research and Development 08/2006; · 0.72 Impact Factor
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A.W. Topol,
D.C. La Tulipe,
L. Shi,
S.M. Alam, D.J. Frank,
S.E. Steen,
J. Vichiconti,
D. Posillico,
M. Cobb,
S. Medd, [......],
R.A. Conti,
D.M. Canaperi,
L. Deligianni,
A. Kumar,
K.T. Kwietniak,
C. D'Emic,
J. Ott,
A.M. Young,
K.W. Guarini,
M. Ieong
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ABSTRACT: We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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D.M. Fried,
J.M. Hergenrother,
A.W. Topol,
L. Chang,
L. Sekaric,
J.W. Sleight,
S.J. McNab,
J. Newbury,
S.E. Steen,
G. Gibson, [......],
J.A. Ott,
C.D. Adams,
T.J. Dalton,
R. Nunes,
D.R. Medeiros,
R. Viswanathan,
M. Ketchen,
M. Ieong,
W. Haensch,
K.W. Guarini
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ABSTRACT: A 0.143 μm<sup>2</sup> 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V<sub>T</sub>) and cell beta ratio (β) are optimized for cell stability at these aggressive ground rules. The 0.143 μm<sup>2</sup> 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V<sup>DD</sup>=1.0 V.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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ABSTRACT: Band-to-band tunneling was studied experimentally in ion-implanted PN junction diodes with profiles representative of present and future silicon CMOS transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of CV characteristics, and compared to SIMS analysis. When tunneling current was plotted against distance (tunneling distance, corrected for band curvature) a quasi-universal exponential reduction of tunneling current vs. tunneling distance was found with an attenuation length of 0.38 nm, and an extrapolated tunneling current at zero tunnel distance of 5.3×10<sup>7</sup> A/cm<sup>2</sup> at 300 K. These results were used to estimate drain-substrate currents in future scaled CMOS, and it was concluded that it will be challenging to make the ITRS 2002 roadmap projections on leakage current for the low operating power and low standby power options without more innovation and device design changes.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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K.W. Guarini,
A.W. Topol,
M. Ieong,
R. Yu,
L. Shi,
M.R. Newport, D.J. Frank,
D.V. Singh,
G.M. Cohen,
S.V. Nitta,
D.C. Boyd,
P.A. O'Neil,
S.L. Tempest,
H.B. Pogge,
S. Purushothaman,
W.E. Haensch
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ABSTRACT: We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.
Electron Devices Meeting, 2002. IEDM '02. International; 01/2003
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ABSTRACT: This paper presents a dual supply voltage strategy for reduction of the total (static and dynamic) power of high performance CMOS processors. By expressing CMOS delay, static power, and dynamic power in terms of the power supply voltage V<sub>DD</sub> and threshold voltage V<sub>T</sub>, an optimization procedure that takes the circuit activity factor into account is performed to find the V<sub>DD</sub> and V<sub>T</sub> for minimum total power at given performance levels. It is shown that 50% power reduction or 20% performance enhancement can be attained by adopting both a low (0.5 V) supply voltage for high-activity circuits and a high (1.2 V) supply voltage for low-activity circuits in a 100 nm-node CMOS technology.
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
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D.J. Frank
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ABSTRACT: This paper argues that the end of scaling is full technology optimization, and shows how application-dependent power dissipation constraints can be incorporated into system-level analyses to yield optimal device and technology design parameters. A new optimization criteria, ROI (Return on Investment), is introduced, and dependencies on underlying assumptions are investigated.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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ABSTRACT: This paper presents the current state of understanding of the
factors that limit the continued scaling of Si complementary
metal-oxide-semiconductor (CMOS) technology and provides an analysis of
the ways in which application-related considerations enter into the
determination of these limits. The physical origins of these limits are
primarily in the tunneling currents, which leak through the various
barriers in a MOS field-effect transistor (MOSFET) when it becomes very
small, and in the thermally generated subthreshold currents. The
dependence of these leakages on MOSFET geometry and structure is
discussed along with design criteria for minimizing short-channel
effects and other issues related to scaling. Scaling limits due to these
leakage currents arise from application constraints related to power
consumption and circuit functionality. We describe how these constraints
work out for some of the most important application classes: dynamic
random access memory (DRAM), static random access memory (SRAM),
low-power portable devices, and moderate and high-performance CMOS
logic. As a summary, we provide a table of our estimates of the scaling
limits for various applications and device types. The end result is that
there is no single end point for scaling, but that instead there are
many end points, each optimally adapted to its particular applications
Proceedings of the IEEE 04/2001; · 6.81 Impact Factor
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ABSTRACT: MOSFET threshold voltage (V<sub>T</sub>) variation due to random
variations in the number and position of dopant atoms is an increasingly
important problem as device dimensions shrink and has received
increasing attention. This paper describes a recently implemented 3-D
Monte Carlo approach for modeling random dopant fluctuation effects in
MOSFETs. We also describe the results of simulating dopant fluctuation
effects in several different MOSFET structures
Computational Electronics, 2000. Book of Abstracts. IWCE Glasgow 2000. 7th International Workshop on; 02/2000
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ABSTRACT: This paper examines the apparent limits, possible extensions, and
applications of CMOS technology in the nanometer regime. Starting from
device scaling theory and current industry projections, we analyze the
achievable performance and possible limits of CMOS technology from the
point of view of device physics, device technology, and power
consumption. Various possible extensions to the basic logic and memory
devices are reviewed, with emphasis on novel devices that are
structurally distinct front conventional bulk CMOS logic and memory
devices. Possible applications of nanoscale CMOS are examined, with a
view to better defining the likely capabilities of future
microelectronic systems. This analysis covers both data processing
applications and nondata processing applications such as RF and imaging.
Finally, we speculate on the future of CMOS for the coming 15-20 years
Proceedings of the IEEE 05/1999; · 6.81 Impact Factor
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ABSTRACT: This paper presents a new 3D Monte Carlo approach for modeling
random dopant fluctuation effects in MOSFETs. The method takes every
silicon atom in the device into account and is generally applicable to
arbitrary nonuniform doping profiles. In addition to body dopant
fluctuations, the effect of source-drain dopant fluctuations on
short-channel threshold voltage is studied for the first time. The
result clearly indicates the benefit of retrograde body doping and
shallow/abrupt source-drain junctions. It also quantifies the magnitude
of threshold voltage variations due to discrete dopant fluctuations in
an optimally designed 25 nm MOSFET
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
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ABSTRACT: Si CMOS technology has steadily grown in importance for the past 30 years until it is now the dominant logic technology in the electronics industry. This talk will briefly describe the current state of Si CMOS and will then concentrate on where it appears to be headed in the next decade or so
Device Research Conference Digest, 1999 57th Annual; 02/1999
