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ABSTRACT: This paper presents a thorough investigation of the main variability effects in nanoscale nand Flash memories, considering their impact on device operation by means of a statistical compact model for the memory array. The compact model allows the accurate simulation not only of the nand string current in read conditions, including parasitic capacitive couplings among neighboring cells, but also of cell program and erase. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of both neutral and programmed cell threshold voltage is obtained for state-of-the-art and next-generation technology nodes. The good agreement between modeling and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on nand technology design.
IEEE Transactions on Electron Devices 09/2011; · 2.32 Impact Factor
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ABSTRACT: A physics-based compact model describing the electrothermal behavior of polysilicon resistors considering both the roles of the grain-boundary potential barriers and the transport inside the silicon decananocrystallites is presented. The model accurately captures the resistivity modulation as a function of temperature, dopant concentration, and grain size, including also the self-heating-induced nonlinear effects in the current-voltage relationship. An accurate agreement of the model against the experimental characterization is reported.
IEEE Electron Device Letters 12/2010; · 2.85 Impact Factor
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ABSTRACT: The conduction process of phase-change-memory (PCM) devices in the amorphous high-resistance state is described by a trap-limited transport model. Based on numerical simulations of the barrier lowering in a potential landscape due to localized charged states, we propose a physically based analytical hopping model accounting for the different voltage dependence of current characteristics in the low- and high-field regimes. The analytical model is able to accurately describe, with the same set of parameters, the experimental behavior of both the temperature-dependent I - V curves and the voltage-dependent activation energy for conduction. Comparison with experimental data is provided, demonstrating the physical consistency of the proposed model.
IEEE Electron Device Letters 10/2010; · 2.85 Impact Factor
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ABSTRACT: This letter presents a detailed experimental investigation of the erase transients of decananometer NAND Flash memories, showing a drop and then a recovery of the erase efficiency as the erase bias is increased. The modulation of the erase efficiency is studied as a function of the erase time, temperature, and the number of applied pulses: Longer erase times or higher temperatures are shown to reduce the efficiency drop, while this is enhanced when the erase pulse is split into a sequence of short pulses. Experimental evidences are explained as a result of the deep-depletion condition that exists in the floating-gate polysilicon for moderate erase biases and short erase times, reducing the electric field in the tunnel oxide and the electron-tunneling current discharging the floating gate.
IEEE Electron Device Letters 08/2010; · 2.85 Impact Factor
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ABSTRACT: This work investigates the variability effects on the threshold voltage distribution of deca-nanometer NAND Flash memories. Different sources of variability have been considered, evaluating their impact on the neutral, programmed and erased distributions. A compact model that is able to account for the variability effects on the array performance and reliability is presented and used. Monte Carlo simulations have been employed to analyze the contributions of variability when technology nodes scale down and to compare the intrinsic variability with the electron injection statistical fluctuations. A good agreement with experimental data is reached, opening the application of the proposed methodology to investigate the reliability impact of variability on future technology nodes.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: In this work a new analytical transport model for the readout region of amorphous GST is proposed. The model is employed to assess, through Monte Carlo (MC) simulations, the sources of variability responsible for the width and shape of the readout current distributions of reset bits. The correlation between transport mechanisms and the statistical spread is highlighted, also considering the reset pulses dependence. Furthermore, the temperature effect on the reset bits is addressed. The statistical characterization results are discussed within the framework of the proposed model.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: The capability to handle multi-level cells is an appealing challenge to reach a high degree of integration also in the field of phase change memories (PCMs). To this aim, tight current (or bit) distributions are needed so as to allocate all programmed levels in the allowed window. As opposed to the above requirement, technology driven spreads tend to increase when the memory cell shrinks to nanoscale sizes, and even atomic scale fluctuations can play an important role. In this scenario, the present work provides a new physically based approach that allows describing the statistical spread for the bit distributions of PCM arrays through a viable and flexible SPICE-like model.
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
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ABSTRACT: Low-frequency noise has been experimentally characterized in the disordered insulating phase of chalcogenide-based phase-change memory (PCM) devices. An analytical model of noise based on the two-level systems (TLS) theory has been developed. In this framework we suggest that the origin of the 1/f<sup>γ</sup> noise in the conductivity of amorphous chalcogenides has to be ascribed to the TLS-induced fluctuations of the mean trap energy in the material. The model allows to quantitatively account for noise magnitude dependence on both voltage and temperature in the readout region of the memory device. Besides, our equations well describe the noise behavior as a function of the drift phenomenon, coherently with existing structural relaxation theories. Measurements and model results show that the noise-to-signal ratio (N/S) in the readout region of the cell is constant with respect to bias; hence there is no particular readout voltage that minimizes N/S. Furthermore, the analysis of noise data with cell scaling confirms that noise in PCMs is mainly due to the bulk properties of the chalcogenide employed rather than to interfacial effects.
Journal of Applied Physics 10/2009; · 2.17 Impact Factor
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ABSTRACT: Low-frequency noise in PCM devices is experimentally investigated providing a new physical model for the amorphous GST (Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>) material. Noise intensity is characterized and modelled as a function of bias, temperature and size. Findings from 1/f noise analysis are used to understand the drift mechanism of the amorphous state resistance.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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ABSTRACT: In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.
IEEE Electron Device Letters 11/2008; · 2.85 Impact Factor
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ABSTRACT: Tight bits distribution is a must to fabricate multi-level Non-Volatile Memory (NVM) technology needed to reach a high degree of integration. On the contrary, the Non-Volatile cell shrink to nanoscale sizes produces a huge modulation in the device performances when atomistic scale fluctuations occur. The present work provides a new physically-based model allowing describing, through a simple analytical approach, the statistical V<sub>TH</sub> spread for Floating Gate based NVM technologies with nanoscale dimensions.
Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on; 10/2008
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ABSTRACT: In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.
IEEE Electron Device Letters 01/2008; 29:1152. · 2.85 Impact Factor
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ABSTRACT: The magnitude of a random telegraph signal (RTS) in nanoscale floating-gate devices has been experimentally investigated as a function of carrier concentration. Discrete current switching, which is caused by a single trap, has been found to be almost one order of magnitude higher with respect to what was predicted by the classical theory of carrier number and correlated mobility fluctuations. Nevertheless, the trap signature well fits the typical SiO<sub>2</sub> trap spectroscopy. In addition, the rigid shift between the transfer curves related to filled- and empty-trap state, together with the normalized current fluctuation dependence on the channel carrier density, suggests that a pure number fluctuation is the correct theoretical interpretative framework. Thus, we propose a possible physical explanation for such a giant RTS on the basis of a quasi-1-D current filamentation.
IEEE Electron Device Letters 01/2008; · 2.85 Impact Factor
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ABSTRACT: In this letter, we show a compact model that describes the main electrical features of phase change memory (PCM) devices. The model coherently reproduces the behavior of both SET and RESET states with the description of the physics of involved phenomena for different bias and temperature conditions. For arbitrary programming pulses, the model is able to generate intermediate states with mixed phase distributions and, thus, with resistance values between the SET and RESET ones. The proposed model is therefore a precious tool for the design of multilevel PCM applications.
IEEE Electron Device Letters 12/2007; · 2.85 Impact Factor
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ABSTRACT: The continuous scaling of physical dimensions has strongly increased circuit performance variability and the traditional corner-case methodology is becoming unreliable. As a consequence, there is an urgent need for new and more accurate statistical models. In this scenario, the purpose of this paper is twofold: 1) to give the reader the basic concepts of statistical modeling, and 2) to discuss a viable statistical approach that could be adopted into a traditional IC design flow for the next technology generations.
Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.; 08/2007
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ABSTRACT: In the present work we present a compact model, oriented to the SPICE-like simulation, that pictures the electrical behavior of integrated resistors fabricated in CMOS technologies. The model accounts for the main electrical features of integrated resistors such as the depletion effects, the head resistance contribution, the velocity saturation and the temperature behavior also including possible self-heating phenomena. It has been validated by considering a wide fan of integrated resistors: n-and p-type, diffused, poly silicon devices. It could be a precious tool for design in analog application, where a very accurate description of the electrical behavior is needed.
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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ABSTRACT: In this paper, we will present the basic structure and the parameter extraction procedure for a compact model of a NAND Flash memory string working in Spice-like circuit simulators. To the author knowledge, this is the first Spice-like model of a NAND Flash memory string. This model is modular and simple to be implemented. It will allow accurately reproducing both DC and transient behavior of NAND Flash memories without increasing computational effort, thus becoming an indispensable tool for designers to optimize circuits especially in multi-level applications.
International Conference on Simulations of Semiconductor Processes and Devices, Austria; 01/2007
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ABSTRACT: In this paper we present the first inherently single-piece model describing the phase change memories (PCM) electrical behavior. The model correctly reproduces for all bias and temperature conditions the behavior of both SET and RESET states, including the exponential pre-switching regime and the S-shaped negative differential resistance region. The model responds with resistance changes to different programming (SET or RESET) pulses, and retains the stored data. The proposed model provides a precious tool for the design of non-volatile memory products based on the new phase change memory concept
Simulation of Semiconductor Processes and Devices, 2006 International Conference on; 10/2006
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ABSTRACT: Low-frequency noise spectral density in chalcogenide-based phase-change memory cells has been measured, discussing the role of trapping centers and static disorder as responsible for a noise level in the vitreous insulating state two orders of magnitude higher than in the ordered conducting polycrystalline one. The magnitude of 1/f noise has been also studied as a function of the applied voltage and exploited to experimentally investigate the transport mechanisms in chalcogenide alloys, showing that the exponential increase of noise spectral density with voltage can be quantitatively explained by considering an avalanchelike multiplication phenomenon.
Applied Physics Letters 06/2006; 88(26):263506-263506-3. · 3.84 Impact Factor
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ABSTRACT: The mechanical stress induced by shallow trench isolation (STI) has been characterized by using complementary techniques: 1) TCAD simulation compared with UV-muRaman data to determine the lattice misfit strain; 2) full band Monte Carlo simulation and electrical measurements to study the impact on the transport properties. For the first time, an iterative methodology emphasising the synergy among these techniques is presented. The excellent agreement with our electrical data demonstrated that our methodology is a powerful and useful tool to predict the performance of devices with a controlled stress
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
