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ABSTRACT: The electrical properties and high-field reliability of HfTa-based gate-dielectric metal–oxide–semiconductor (MOS) devices
with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON
stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent
thickness (∼1.1nm), and high dielectric constant (∼20). All of these should be attributed to the blocking role of the ultrathin
AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively
suppressing the unintentional formation of unstable poor-quality low-k GeO
x
and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high-k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.
Applied Physics A 04/2012; 99(1):177-180. · 1.63 Impact Factor
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04/2012; , ISBN: 978-953-51-0512-1
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ABSTRACT: A direct-write lithographic technique for the fabrication of micro-lens arrays with an ultraviolet (UV) micro-light-emitting diode (LED) array serving as an exposure source is reported. Polymer microlens arrays of high optical quality have been fabricated on the sapphire side of a flip-chip truncated-conic (TC) LED. The properties of the lenses are evaluated by optical microscopy and atomic force microscopy. The determined focal length is close to the predicted value. The effects of microlens integration on the optical properties of the LED are investigated.
IEEE Photonics Technology Letters 09/2011; · 2.19 Impact Factor
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ABSTRACT: TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N <sub>2</sub> to suppress the growth of unstable GeO <sub> x </sub> at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×10<sup>11</sup> cm <sup>-2</sup> eV ) , small gate leakage current ( 8.6×10<sup>-4</sup> A cm <sup>-2</sup> at V <sub> g </sub>- V <sub> fb </sub>=1 V ), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet- N <sub>2</sub> anneal can significantly suppress the growth of unstable low-k GeO <sub> x </sub> .
Applied Physics Letters 06/2011; · 3.84 Impact Factor
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ABSTRACT: The influence of octadecyltrichlorosilane (OTS) surface modification of a gate dielectric on the electrical properties of polymer thin-film transistors based on poly(3-hexylthiophene) is investigated by using capacitance-voltage analysis. Results show that surface modification using OTS can effectively increase the field-effect mobility in the saturation region by almost two orders of magnitude to 2 × 10<sup>2</sup> cm<sup>2</sup>/V · s and improve the stability of the devices under gate-bias stress. Capacitance-voltage (C-V) analysis for the metal-polymer-oxide-silicon structures indicates that the frequency-dependent behavior of the C-V characteristics is related to the long relaxation time of the charge carriers in the polymer bulk rather than the trapping effect at the dielectric/ polymer interface, and the performance improvement of the de vices is attributed to a reduction of localized charges in the poly mer bulk.
IEEE Transactions on Device and Materials Reliability 04/2011; · 1.54 Impact Factor
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ABSTRACT: An InGaN/GaN light-emitting diode (LED) chip mounted in a vertical configuration (vmLED) is demonstrated, exhibiting significant enhancement to light extraction, compared with a LED mounted in a conventional planar geometry. By flipping the chip orthogonally, two large illumination surfaces of the device are exposed for direct light extraction. Comparisons, through ray-trace modeling and experiment data with conventional surface-mounted LEDs, indicate that the vmLEDs achieve superior light extraction efficiency. A sapphire-prism-mounted vmLED is further proposed to improve heat sinking, which is well suited for higher current operations.
IEEE Transactions on Electron Devices 03/2011; · 2.32 Impact Factor
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ABSTRACT: Ge MOS capacitors with tri-layer gate dielectric are proposed by using GeON interlayer, TaON sandwich layer, and HfTiON high-k dielectric. Very small capacitance equivalent thickness (0.79~0.91 nm) is achieved. Experimental results show that the NO pretreated sample exhibits the best electrical properties, such as low interface-state density (5.4 × 10<sup>11</sup> cm<sup>-2</sup> eV<sup>-1</sup>), low gate leakage current density (~ 3.16 × 10<sup>-4</sup> Acm<sup>-2</sup> at V<sub>g</sub> - V<sub>fb</sub> = 1 V) and high device reliability. All of these should be attributed to the facts that the NO nitridation could form a GeON interlayer with suitable N content and thus provide an excellent GeON/Ge interface with strong Ge-N bonds, while the TaON sandwich layer could separate Hf and Ge, thus effectively preventing the reaction between them and improving the interface quality and electrical properties of the devices.
IEEE Electron Device Letters 03/2011; · 2.85 Impact Factor
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ABSTRACT: Pentacene organic thin-film transistors (OTFTs) with HfLaO high-κ gate dielectric were fabricated. The dielectric was prepared by a sputtering method and then annealed in N<sub>2</sub>, NH<sub>3</sub>, O<sub>2</sub>, or NO at 400 °C. The carrier mobility of the NH<sub>3</sub>-annealed OTFT could reach 0.59 cm<sup>2</sup>/V · s, which is higher than those of the other three devices. Moreover, the NH<sub>3</sub>-annealed OTFT obtained the smallest subthreshold swing of 0.26 V/dec among them. Furthermore, 1/f noise measurement indicated that the NH<sub>3</sub>-annealed OTFT achieved the smallest 1/f noise. All these should be attributed to the improved interface between the gate dielectric and the organic semiconductor associated with the passivation effects of the NH<sub>3</sub> annealing on the dielectric surface.
IEEE Electron Device Letters 02/2011; · 2.85 Impact Factor
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ABSTRACT: Pentacene OTFTs with HfLaO or HfO<sub>2</sub> as gate dielectric were fabricated. The dielectrics were prepared by sputtering method and then annealed in NH<sub>3</sub> at 400 oC. The k value for the HfLaO and HfO<sub>2</sub> films amounted to 12.3 and 11.8 respectively. Both of the OTFTs could operate with a supply voltage of -5 V. The mobility of the OTFT with HfLaO gate dielectric was 0.688 cm<sup>2</sup>/Vs, which was much higher than that of the OTFT with HfO<sub>2</sub> gate dielectric. Moreover, the HfLaO-based OTFT obtained smaller sub-threshold swing, larger drive current and larger on/off current ratio than the HfO<sub>2</sub>-baesd OTFT. The superior performance of the HfLaO-based OTFT is due to its better interfacial characteristics between the dielectric and the organic semiconductor. SEM images revealed that the pentacene film on HfLaO was more uniform and its grains were larger. C-V measurement indicated that Au-pentacene-HfLaO-Si structure displayed less hysteresis than Au-pentacene-HfO<sub>2</sub>-Si structure.
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of; 01/2011
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ABSTRACT: The light extraction efficiencies of InGaN/GaN blue light-emitting diodes (LEDs) of different geometries ranging from a triangle to a decagon have been simulated by ray-tracing. The conventional rectangular LED was found to be the most inefficient among the investigated polygons, and light extraction through the device sidewalls was the key factor. The results were experimentally verified by fabricating LEDs shaped into polygons by nanosecond-pulsed laser micromachining, which proved the simulated results. The mechanism of light extrac-tion in polygonal LEDs is discussed in detail.
Journal of Applied Physics 07/2010; 108(2):023110-023110-5. · 2.17 Impact Factor
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ABSTRACT: The electrical properties of n-Ge metal-oxide-semiconductor (MOS) capacitors with HfO2/LaON or HfO2/La2O3 stacked gate dielectric (LaON or La2O3 as interlayer) are investigated. It is found that better electrical performances, including lower interface-state density, smaller gate leakage current, smaller capacitance equivalent thickness, larger k value, and negligible C-V frequency dispersion, can be achieved for the MOS device with LaON interlayer. The involved mechanism lies in that the LaON interlayer can effectively block the interdiffusions of Ge, O, and Hf, thus suppressing the growth of unstable GeOx interlayer and improving the dielectric/Ge interface quality.
Applied Physics Letters 07/2010; 97(2):022903-022903-3. · 3.84 Impact Factor
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ABSTRACT: The effects of hafnium oxide (HfO<sub>2</sub>) gate dielectric annealing treatment in oxygen (O<sub>2</sub>) and ammonia (NH<sub>3</sub>) ambient on the electrical performance of polymer thin-film transistors (PTFTs) based on poly(3-hexylthiophene) are investigated. The PTFTs with HfO<sub>2</sub> gate dielectric and also octadecyltrichlorosilane surface modification, prepared by spin-coating process, exhibit good performance, such as a small threshold voltage of -0.5 V and an operating voltage as low as -4 V. Results indicate that the PTFT with NH<sub>3</sub>-annealed HfO<sub>2</sub> shows higher carrier mobility, larger on/off current ratio, smaller subthreshold swing, and lower threshold voltage than the PTFT with O<sub>2</sub>-annealed HfO<sub>2</sub>. Capacitance-voltage analysis for metal-polymer-oxide-silicon structures indicates that the better electrical performance of the PTFT with NH<sub>3</sub>-annealed HfO<sub>2</sub> is attributed to improved dielectric/polymer interface and reduced series resistance in the transistor.
IEEE Transactions on Device and Materials Reliability 07/2010; · 1.54 Impact Factor
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ABSTRACT: We report on white light-emitting diodes (LEDs) with a truncated-conical (TC) geometry produced by laser micromachining. A blue LED was shaped into a circular disc with 50??-inclined sidewall using a modified laser micromachining setup. A layer of Al was coated onto the inclined sidewall and the bottom surface to form an integrated reflector. Due to the highly reflective mirror, laterally propagating photons are redirected into the upward direction, contributing to an increase of 21.7% of light intensity in the normal direction. With quantum dots applied to the surface, white light emission from this TC-LED structure demonstrated a 37% enhancement in color uniformity, compared with a conventional device.
IEEE Photonics Technology Letters 05/2010; · 2.19 Impact Factor
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ABSTRACT: We report on a direct-write lithographic technique for the fabrication of micro-lens arrays with an ultraviolet (UV) micro-light-emitting diode (LED) array, serving as an exposure source. Owing to the Lambertian emission distribution of LEDs, the exposed UV sensitive coating (UV epoxy) adopts the same profile, resulting in spherical lenses being formed naturally, without further reflow. This technique is distinctive from conventional UV curing method and possesses many advantages, including simplicity of processing, allows control of the dimensions of micro-lenses through process parameters, and is readily scalable. Micro-lens arrays of high optical quality have been fabricated by this method. The properties of the lenses are evaluated by optical microscopy and atomic force microscope. The determined focal length is close to the predicted value. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
physica status solidi (c) 04/2010; 7(7‐8):2174 - 2176.
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ABSTRACT: Although InGaN/GaN green light-emitting diodes (LEDs) are widely available, it is still challenging to grow green LED structures for emission at longer wavelengths due to the difficulty associated with the incorporation of In. The higher concentration of In may also affect the performance and reliability of the device. The reliability of green GaN LEDs with three different indium doping concentrations, with centre-wavelength of 520 nm, 540 nm and 550 nm, is studied in this paper. The electrical properties, including I-V characteristics, leakage current and 1/f noise were measured. The optical performance of the devices was also evaluated. The devices were subsequently subjected to a 1000 hours continuous stress test. The defect densities of the LED structures were also determined. Our results show that the 520 nm LED, which contains the lowest indium concentration in its quantum wells, produces highest optical output power at 20 mA. It also degrades slower than 540 nm and 550 nm LEDs.
Journal of Physics Conference Series 02/2010; 209(1):012065.
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ABSTRACT: Thin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La<sub>2</sub>O<sub>3</sub> and Ti targets under different Ar/N<sub>2</sub> ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N<sub>2</sub> ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent thickness, and best electrical characteristics, including low interface-state density, small C-V hysteresis and low gate leakage current. This is attributed to the fact that a suitable N content in LaTiON can effectively suppress the growth of low-k GeO<sub>x</sub> interfacial layer between LaTiON and Ge substrate.
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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ABSTRACT: In this work, Al/HfTiON/n-Si capacitors with different sputtering and annealing temperatures are studied. Larger accumulation capacitance and flat-band voltage are observed for samples with higher sputtering or post-deposition annealing temperature. Gate conduction mechanisms are only affected by sputtering temperature slightly. The flat-band voltage shift and interface-state density at midgap under high-field gate injection and substrate injection are investigated, and the results imply electron detrapping in the gate dielectric.
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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ABSTRACT: In this work, Ge MOS capacitors with Y<sub>2</sub>O<sub>3</sub> gate dielectric were fabricated. The effects of annealing in N<sub>2</sub>, NH<sub>3</sub> O<sub>2</sub> or NO ambient were investigated. Experimental results demonstrated that the NO annealing could improve both electrical properties and reliability of Ge MOS devices with Y<sub>2</sub>O<sub>3</sub> dielectric. On the other hand, the NH<sub>3</sub> annealing resulted in H-related traps while the O<sub>2</sub> annealing suffered from extra GeO<sub>x</sub> growth, thus both degrading the performance of the devices.
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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ABSTRACT: OTFTs with P3HT as organic semiconductor and HfTiO as gate dielectric have been studied in this work. The HfTiO dielectric film was prepared by RF sputtering of Hf and DC sputtering of Ti at room temperature. Subsequently, the dielectric film was annealed in an NH<sub>3</sub> or N<sub>2</sub> ambient at 200°C. Then a layer of OTS was deposited by spin-coating method to improve the surface characteristics of the gate dielectric. Afterwards, P3HT was deposited by spin-coating method. The OTFTs were characterized by I-V measurement and 1/f noise measurement. The OTFT with gate dielectric annealed in NH<sub>3</sub> displays higher carrier mobility, smaller threshold voltage, smaller sub-threshold swing, and lower 1/f noise level than the OTFT annealed in N<sub>2</sub>. Moreover, the HfTiO dielectric film annealed in NH<sub>3</sub> shows higher dielectric constant. In summary, HfTiO film annealed in NH<sub>3</sub> at low temperature is a promising candidate to act as the gate dielectric of high-quality low-voltage OTFTs.
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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ABSTRACT: In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interlayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interlayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current.
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
