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ABSTRACT: In this paper, the FER is shown to be a possible candidate for ESD protection in deeply scaled SOI technology. I<sub>t2</sub> of above 50 mA/μm and capacitance below 0.6 fF/μm are achieved. Despite the FER's higher resistivity than SOI diode, its major advantage is the dual-directional current shunting capability, such that ESD protection between I/O pads and power buses can be achieved with a single-device solution at the pad instead of several devices. Therefore, this device expands the conventional ESD design space for trading off parameters such as resistivity, I<sub>leak</sub> and capacitance. Results from measurements and TCAD simulations further instantiate the advantages of the FERs in current and future SOI technologies. For future technologies such as ultra-thin-film SOI and FinFET, better gate controllability can be achieved to sustain the inversion regions. Thus, the well doping can be increased to lower the resistivity, making the FER more suitable for I/O protection.
SOI Conference (SOI), 2010 IEEE International; 11/2010
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ABSTRACT: This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a device's performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme.
IEEE Transactions on Electron Devices 04/2010; · 2.32 Impact Factor
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ABSTRACT: In this paper, the improved field-effect diode (FED) has been characterized and modeled in 45 nm silicon-on-insulator (SOI) technology. It has been experimentally shown to be suitable for pad-based local clamping under normal supply voltage (V<sub>dd</sub>) range (below 1 V) in high-speed integrated circuits. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device's performance in charged device model (CDM) ESD events. The FED's advantages in improving transient turn-on behavior and reducing DC leakage current have been analyzed and compared with other silicon-controlled-rectifier (SCR)-based SOI device variations. Technology CAD (TCAD) simulations are used to interpret the turn-on behavior and the physical effects. Process tradeoffs have been evaluated. The work prepares the device for being directly applied to high-speed input/output (I/O) circuit and it addresses the severe challenge in CDM ESD protection. The improved device enables the adoption of local clamping scheme that expands the ESD design window.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
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ABSTRACT: In this paper, we present a comparison of the turn-on voltage between SOI-SCR, and the novel DWFED structure. We show that DWFED can achieve faster turn-on, protecting the low voltage devices more effectively. Using the pulse waveforms, we justify the use of a gate trigger circuit for the DWFED to reduce the transient spikes under faster CDM pulses.
SOI Conference, 2008. SOI. IEEE International; 11/2008
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ABSTRACT: This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45 nm silicon on insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th; 10/2008
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M.M. Pelella,
Darin Chan,
S. Kruegel,
K. Frohberg,
J. Rivers,
T. Heller,
R. Richter,
N. Rodriguez,
R Klein,
J Zhou, [......],
J. Working,
C. Schwan,
M. Horstmann,
B. En,
K. Wieczorek,
D. Greenlaw,
T. Heidel,
V. Heinig,
J. Miethke,
N. Kepler
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ABSTRACT: A new device structure to mitigate plasma charging damage in advanced SOI technologies has been demonstrated that can be easily incorporated into modern-day, as well as future-scaled microprocessor designs. This novel structure offers improved product yields and also mitigates "walking- wounded" device characteristics that oftentimes plague the operation and speed grades of advanced microprocessors with threshold voltage shifts and increased leakage currents.
SOI Conference, 2007 IEEE International; 11/2007
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ABSTRACT: The double well field effect diode (DWFED), an SOI SCR-like device for ESD protection of I/O circuits, is presented. The effect of device and process parameters on the diode on-voltage is examined, and the TLP and VFTLP characteristics of the DWFED are compared with those of the SOI lateral diode. It is shown how to use the DWFED for local clamping ESD protection, with a diode-like It2 level.
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD; 10/2007
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ABSTRACT: In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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ABSTRACT: This paper presents a new integrated silicon-on-insulator (SOI) substrate-diode (SUBD) structure for an electrostatic-discharge (ESD) protection of the SOI I/O circuits. The diode is built under the buried oxide, within the substrate region of the SOI wafer, without additional steps to the conventional SOI CMOS process. This paper shows that the ESD protection level can reach four times the level of the standard SOI lateral-diode structure. This paper presents the device and process simulation results to demonstrate the effect of self-heating in both the standard SOI lateral and substrate diodes, and to demonstrate how to optimize the SUBD structure using a deep n-well implant
IEEE Transactions on Device and Materials Reliability 07/2006; · 1.54 Impact Factor
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ABSTRACT: In this work, we describe novel self-aligned diode and resistor structures and their process integration into an advanced 90nm SOI technology. Their superior device characteristics over conventional device structures built within the SOI film is described.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
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J.-S. Goo,
J.X. An,
C. Thuruthiyil,
T. Ly,
Q. Chen,
M. Radwin,
Zhi-Yuan Wu,
M.S.L. Lee,
L. Zamudio,
J. Yonemura,
F. Assad, M.M. Pelella,
A.B. Icel
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ABSTRACT: This work presents explicit fitting guidelines for AC and DC characteristics, specifically focused on accurate modeling of the history effects in the PD-SOI CMOS circuits. The body potential of the PD-SOI device is primarily determined by the diode current, gate-body current, impact ionization current, junction capacitance, and gate-body capacitance. This paper also discusses artifacts associated with the parasitic currents and highly-resistive thin-body of the PD-SOI.
SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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ABSTRACT: The switching-mode dependence of inductive noise on the power bus lines has been investigated. As the maximum operation frequency of the very large-scale integration is determined by the slowest response in the critical path, suppression of inductive noise in power lines is crucial. Circuits with 50% duty cycle are almost free of inductive noise. Contrarily, the low duty cycle circuits are highly subject to the inductive noise thus the decoupling capacitor needs to be carefully implemented, considering the line inductance and effective frequency. The conventional "10× of switching-capacitor" rule-of-thumb is not applicable to decoupling capacitor implementation and can cause worse inductive noise than a "no capacitor" situation.
IEEE Electron Device Letters 06/2004; · 2.85 Impact Factor
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ABSTRACT: We have shown that not only recombination lifetime, but also gate tunneling is an important component in determining the steady-state body potential in scaled PDSOI MOSFETs. Both elements affect the lateral bipolar induced charge dump current during pass gate transient operation. Increase in the gate tunneling current and reduction of the recombination lifetime have resulted in the displacement current from the drain and gate capacitances to be the dominant component of the charge dump current.
SOI Conference, IEEE International 2002; 11/2002
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ABSTRACT: The performance advantage of floating-body (FB) partially depleted
(PD) SOI CMOS technology is analyzed via device/circuit simulations,
with emphasis on providing insight into the physical mechanisms
underlying the advantage. Comparisons of predicted propagation delay of
contemporary and scaled FB PD/SOI CMOS, including hysteresis, with those
of the bulk-Si and body-tied-to-source/SOI counterparts, all with
controlled off-state current, are made, and the impact of junction
capacitance, the kink effect, and capacitive-coupling effects are
quantified. Scaling the technologies is shown to diminish the
performance advantage of FB PD/SOI CMOS, but this tendency can be
mitigated by typically elevated operating temperatures,
stacked-transistor logic, and device-design optimization
IEEE Transactions on Electron Devices 02/2002; · 2.32 Impact Factor
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ABSTRACT: This paper presents a detailed study on the temperature dependence
of the hysteresis effect in static CMOS circuits and
pass-transistor-based circuits with floating-body partially depleted
(PD) silicon-on-insulator (SOI) CMOS devices. Basic physical mechanisms
underlying the temperature dependence of hysteretic delay variations are
examined. It is shown that, depending on the initial state of the
circuit, the initial circuit delays have distinct temperature
dependence. For steady-state circuit delays, the temperature dependence
is dictated solely by the various charge injection/removing mechanisms
into/from the body. The use of the cross-coupled dual-rail configuration
in pass-transistor-based circuits is shown to be effective in
compensating and reducing the disparity in the temperature dependence of
the delays
IEEE Journal of Solid-State Circuits 03/2001; · 3.23 Impact Factor
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M.M. Pelella,
W. Maszara,
S. Sundararajan,
S. Sinha,
A. Wei,
D. Ju,
W. En,
S. Krishnan,
D. Chan,
S. Chan, [......],
M. Fuselier,
R. vanBentum,
G. Burbach,
C. Lee,
G. Hill,
D. Greenlaw,
C. Riccobenc,
O. Karlsson,
D. Wristers,
N. Kepler
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ABSTRACT: The key performance advantages and challenges of SOI CMOS for ULSI
applications are discussed in detail. Included is an insightful analysis
comparing the performance benefits of SOI technologies over its bulk-Si
counterpart. The hysteretic trends of a floating-body PD/SOI inverter
circuit are uniquely characterized using a Teradyne J971 system; and the
charge-dump and self-heating effects are shown to be under control using
an advanced 0.13 μm SOI device technology. Future technology
opportunities are described that could provide a viable roadmap of SOI
technologies to leverage in the future
SOI Conference, 2001 IEEE International; 02/2001
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ABSTRACT: This paper reviews the applications of device modeling, characterization, and simulations of partially depleted (PD) SOI devices and technology for microprocessor designs. SOI-specific effects and characteristics, which make SOI different from bulk MOSFET, are discussed with underlying device physics and insights obtained from simulations using compact model and device simulator. Means for achieving the ultimate goal of SOI device and circuit designs, that is to maximize SOI performance while minimize undesirable effects, are also discussed in the paper
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on; 02/2001
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ABSTRACT: One option to counter the slowing CMOS scaling trend is to reduce the ambient temperature (T) of the semiconductor chip. At low operating T, increased carrier mobility, subthreshold slope, and threshold voltage (V<sub>t</sub>) have been demonstrated for bulk-Si MOSFETs (Sun et al., 1987), thus enhancing drive current, allowing lower-V<sub>t</sub> design, and providing significant improvement in the speed-power performance of the technology, especially for the same-off-current T-scaling scenario (Taur and Nowak, 1997). In this paper, the behavior of floating-body (FB) partially depleted (PD) SOI CMOS is evaluated at low T down to -100°C, which reflects a practical operating temperature range subject to the cost of the required cooling system. Results show that the negative T-coefficient of the FB voltage V<sub>BS </sub>(T) (Pelella et al, 1998) can lead to activation of the parasitic bipolar transistor (BJT), inducing an anomalous subthreshold current characteristic as T is reduced. They further reveal an increasing off-state current (I<sub>off</sub>), below a critical T, which implies a possible limit to the low-T operating range of FB PD/SOI CMOS. However, we show that device optimization can ameliorate this low-T bipolar effect, enabling a lower-T operating range and a significantly enhanced circuit performance
SOI Conference, 2000 IEEE International; 02/2000
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ABSTRACT: In this paper the hysteretic (history-dependent) propagation gate
delay of floating-body (FB) partially depleted (PD) SOI CMOS circuits is
investigated. The change in gate propagation delay with time is examined
with no preconditioning of the floating-body. The simulation-based
analysis includes the sensitivity of the hysteresis to supply voltage,
Wp/Wn (beta ratio), duty cycle, slew rate, output load, and initial
state of the circuit. Basic physical mechanisms underlying the
hysteretic circuit behavior are examined. The results identify the main
contributors and general trends of hysteresis in FB PD/SOI circuits. The
insight gained can ultimately be incorporated into conventional circuit
timing tools. The results also reveal a circuit sizing methodology to
minimize the hysteresis effects in circuits using PD/SOI
technology
VLSI Technology, Systems, and Applications, 1999. International Symposium on; 02/1999
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ABSTRACT: A new methodology to characterize and analyze hysteresis in PD/SOI
CMOS inverter-based circuits, including its true worst case, is defined,
and new insight into the underlying physics is provided. The methodology
is used to explore novel device/circuit designs for controlling
hysteresis as the PD/SOI CMOS technology is scaled to <100 nm
Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999
