M.M. Pelella

Stanford University, Stanford, CA, United States

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Publications (39)30.61 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, the FER is shown to be a possible candidate for ESD protection in deeply scaled SOI technology. I<sub>t2</sub> of above 50 mA/μm and capacitance below 0.6 fF/μm are achieved. Despite the FER's higher resistivity than SOI diode, its major advantage is the dual-directional current shunting capability, such that ESD protection between I/O pads and power buses can be achieved with a single-device solution at the pad instead of several devices. Therefore, this device expands the conventional ESD design space for trading off parameters such as resistivity, I<sub>leak</sub> and capacitance. Results from measurements and TCAD simulations further instantiate the advantages of the FERs in current and future SOI technologies. For future technologies such as ultra-thin-film SOI and FinFET, better gate controllability can be achieved to sustain the inversion regions. Thus, the well doping can be increased to lower the resistivity, making the FER more suitable for I/O protection.
    SOI Conference (SOI), 2010 IEEE International; 11/2010
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    ABSTRACT: This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a device's performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme.
    IEEE Transactions on Electron Devices 04/2010; DOI:10.1109/TED.2009.2039524 · 2.36 Impact Factor
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    ABSTRACT: In this paper, the improved field-effect diode (FED) has been characterized and modeled in 45 nm silicon-on-insulator (SOI) technology. It has been experimentally shown to be suitable for pad-based local clamping under normal supply voltage (V<sub>dd</sub>) range (below 1 V) in high-speed integrated circuits. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device's performance in charged device model (CDM) ESD events. The FED's advantages in improving transient turn-on behavior and reducing DC leakage current have been analyzed and compared with other silicon-controlled-rectifier (SCR)-based SOI device variations. Technology CAD (TCAD) simulations are used to interpret the turn-on behavior and the physical effects. Process tradeoffs have been evaluated. The work prepares the device for being directly applied to high-speed input/output (I/O) circuit and it addresses the severe challenge in CDM ESD protection. The improved device enables the adoption of local clamping scheme that expands the ESD design window.
    Reliability Physics Symposium, 2009 IEEE International; 05/2009
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    ABSTRACT: In this paper, we present a comparison of the turn-on voltage between SOI-SCR, and the novel DWFED structure. We show that DWFED can achieve faster turn-on, protecting the low voltage devices more effectively. Using the pulse waveforms, we justify the use of a gate trigger circuit for the DWFED to reduce the transient spikes under faster CDM pulses.
    SOI Conference, 2008. SOI. IEEE International; 11/2008
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    ABSTRACT: This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45 nm silicon on insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.
    Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th; 10/2008
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    ABSTRACT: A new device structure to mitigate plasma charging damage in advanced SOI technologies has been demonstrated that can be easily incorporated into modern-day, as well as future-scaled microprocessor designs. This novel structure offers improved product yields and also mitigates "walking- wounded" device characteristics that oftentimes plague the operation and speed grades of advanced microprocessors with threshold voltage shifts and increased leakage currents.
    SOI Conference, 2007 IEEE International; 11/2007
  • A.A. Salman, S.G. Beebe, M.M. Pelella
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    ABSTRACT: The double well field effect diode (DWFED), an SOI SCR-like device for ESD protection of I/O circuits, is presented. The effect of device and process parameters on the diode on-voltage is examined, and the TLP and VFTLP characteristics of the DWFED are compared with those of the SOI lateral diode. It is shown how to use the DWFED for local clamping ESD protection, with a diode-like It2 level.
    29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD; 10/2007
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    ABSTRACT: Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.
    37th European Solid State Device Research Conference, 2007. ESSDERC; 10/2007
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    ABSTRACT: In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp
    Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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    ABSTRACT: History effects in 65-nm partially-depleted silicon-on-insulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit designs
    International SOI Conference, 2006 IEEE; 11/2006
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    ABSTRACT: This paper presents a new integrated silicon-on-insulator (SOI) substrate-diode (SUBD) structure for an electrostatic-discharge (ESD) protection of the SOI I/O circuits. The diode is built under the buried oxide, within the substrate region of the SOI wafer, without additional steps to the conventional SOI CMOS process. This paper shows that the ESD protection level can reach four times the level of the standard SOI lateral-diode structure. This paper presents the device and process simulation results to demonstrate the effect of self-heating in both the standard SOI lateral and substrate diodes, and to demonstrate how to optimize the SUBD structure using a deep n-well implant
    IEEE Transactions on Device and Materials Reliability 07/2006; DOI:10.1109/TDMR.2006.876587 · 1.54 Impact Factor
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    ABSTRACT: In this work, we describe novel self-aligned diode and resistor structures and their process integration into an advanced 90nm SOI technology. Their superior device characteristics over conventional device structures built within the SOI film is described.
    SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
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    ABSTRACT: We study the SOI poly-defined lateral diode and its optimization to achieve high second breakdown current, low resistance and low capacitance. A second breakdown current of more than 12 mA/mum is achieved. We present a novel failure mechanism for the diode wherein oxide breakdown occurs during a CDM-like event; floating the poly gate is shown to reduce this susceptibility. We also introduce a biasing method for a gated diode that reduces loading capacitance without impacting ESD performance.
    Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.; 10/2005
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    ABSTRACT: This work presents explicit fitting guidelines for AC and DC characteristics, specifically focused on accurate modeling of the history effects in the PD-SOI CMOS circuits. The body potential of the PD-SOI device is primarily determined by the diode current, gate-body current, impact ionization current, junction capacitance, and gate-body capacitance. This paper also discusses artifacts associated with the parasitic currents and highly-resistive thin-body of the PD-SOI.
    SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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    ABSTRACT: The switching-mode dependence of inductive noise on the power bus lines has been investigated. As the maximum operation frequency of the very large-scale integration is determined by the slowest response in the critical path, suppression of inductive noise in power lines is crucial. Circuits with 50% duty cycle are almost free of inductive noise. Contrarily, the low duty cycle circuits are highly subject to the inductive noise thus the decoupling capacitor needs to be carefully implemented, considering the line inductance and effective frequency. The conventional "10× of switching-capacitor" rule-of-thumb is not applicable to decoupling capacitor implementation and can cause worse inductive noise than a "no capacitor" situation.
    IEEE Electron Device Letters 06/2004; DOI:10.1109/LED.2004.826510 · 3.02 Impact Factor
  • S. Sinha, Meng-Hsueh Chiang, M.M. Pelella
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    ABSTRACT: We have shown that not only recombination lifetime, but also gate tunneling is an important component in determining the steady-state body potential in scaled PDSOI MOSFETs. Both elements affect the lateral bipolar induced charge dump current during pass gate transient operation. Increase in the gate tunneling current and reduction of the recombination lifetime have resulted in the displacement current from the drain and gate capacitances to be the dominant component of the charge dump current.
    SOI Conference, IEEE International 2002; 11/2002
  • Source
    M.M. Pelella, J.G. Fossum
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    ABSTRACT: The performance advantage of floating-body (FB) partially depleted (PD) SOI CMOS technology is analyzed via device/circuit simulations, with emphasis on providing insight into the physical mechanisms underlying the advantage. Comparisons of predicted propagation delay of contemporary and scaled FB PD/SOI CMOS, including hysteresis, with those of the bulk-Si and body-tied-to-source/SOI counterparts, all with controlled off-state current, are made, and the impact of junction capacitance, the kink effect, and capacitive-coupling effects are quantified. Scaling the technologies is shown to diminish the performance advantage of FB PD/SOI CMOS, but this tendency can be mitigated by typically elevated operating temperatures, stacked-transistor logic, and device-design optimization
    IEEE Transactions on Electron Devices 02/2002; DOI:10.1109/16.974755 · 2.36 Impact Factor
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    ABSTRACT: In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 Å-thick silicon film with gate lengths down to 45 nm, using a 16 Å nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 μA/μm and 460 μA/μm were achieved at 20 nA/μm for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA/μm. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.
    VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
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    ABSTRACT: This paper presents a detailed study on the temperature dependence of the hysteresis effect in static CMOS circuits and pass-transistor-based circuits with floating-body partially depleted (PD) silicon-on-insulator (SOI) CMOS devices. Basic physical mechanisms underlying the temperature dependence of hysteretic delay variations are examined. It is shown that, depending on the initial state of the circuit, the initial circuit delays have distinct temperature dependence. For steady-state circuit delays, the temperature dependence is dictated solely by the various charge injection/removing mechanisms into/from the body. The use of the cross-coupled dual-rail configuration in pass-transistor-based circuits is shown to be effective in compensating and reducing the disparity in the temperature dependence of the delays
    IEEE Journal of Solid-State Circuits 03/2001; DOI:10.1109/4.902770 · 3.11 Impact Factor
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    ABSTRACT: This paper reviews the applications of device modeling, characterization, and simulations of partially depleted (PD) SOI devices and technology for microprocessor designs. SOI-specific effects and characteristics, which make SOI different from bulk MOSFET, are discussed with underlying device physics and insights obtained from simulations using compact model and device simulator. Means for achieving the ultimate goal of SOI device and circuit designs, that is to maximize SOI performance while minimize undesirable effects, are also discussed in the paper
    Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on; 02/2001

Publication Stats

319 Citations
30.61 Total Impact Points


  • 2008–2010
    • Stanford University
      • Department of Electrical Engineering
      Stanford, CA, United States
  • 2004–2008
    • Advanced Micro Devices
      Sunnyvale, California, United States
  • 2002
    • AMD
      Sunnyvale, California, United States
  • 1996–2002
    • University of Florida
      • Department of Electrical and Computer Engineering
      Gainesville, Florida, United States